ZHCSLR2C August 2020 – March 2022 TPS61288
PRODUCTION DATA
9.2.2.5 Loop Stability
The TPS61288 requires external compensation, which allows the loop response to be optimized for each application. The COMP pin is the output of the internal error amplifier. An external compensation network, comprised of resistor RC, and ceramic capacitors CC and CP, is connected to the COMP pin.
The power stage small signal loop response of constant off-time (COT) with peak current control can be modeled by Equation 7.
where
- D is the switching duty cycle.
- RO is the output load resistance.
- KCOMP is power stage trans-conductance (inductor peak current / comp voltage), which is 13.5 A/V.
where
- CO is output capacitor.
where
- RESR is the equivalent series resistance of the output capacitor.
The COMP pin is the output of the internal transconductance amplifier. Equation 11 shows the small signal transfer function of compensation network.
where
- GEA is the transconductance of the amplifier.
- REA is the output resistance of the amplifier.
- VREF is the reference voltage at the FB pin.
- VOUT is the output voltage.
- ƒCOMP1, ƒCOMP2 are the frequency of the poles of the compensation network.
- ƒCOMZ is the zero's frequency of the compensation network.
The next step is to choose the loop crossover frequency, ƒC. The higher frequency that the loop gain stays above zero before crossing over, the faster the loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ.
Then set the value of RC, CC, and CP (in Figure 9-1) by following these equations.
where
- ƒC is the selected crossover frequency.
The value of CC can be set by Equation 13.
The value of CP can be set by Equation 14.
If the calculated value of CP is less than 10 pF, it can be left open.
Designing the loop for greater than 45° of phase margin and greater than 10-dB gain margin eliminates output voltage ringing during the line and load transient.