For better output voltage filtering, TI recommends low ESR X5R or X7R ceramic capacitors.

For the output capacitor at the VOUT pin, TI recommends small ceramic capacitors. Place the capacitors as close as possible to the VOUT and GND pins of the device to depress the SW spike. The device can normally work with SW negative spike of -0.7V within 1ns. However, larger negative spike may potentially shoot the MOSFET inside. If, for any reason, the application requires the use of large capacitors that cannot be placed close to the device, the use of a small ceramic capacitor with a capacitance value of 1μF in parallel to the large one is recommended. Place this small capacitor as close as possible to the VOUT and GND pins of the device.

Considering loop stability, for inductance of 4.7 µH, the minimal output capacitor value is 10 μF (effective value). Refer to Table 8-3 for inductor and capacitor combination. Increasing the output capacitor makes the output ripple smaller.

When selecting capacitors, ceramic capacitor’s derating effect under DC bias voltage must be considered. Choose the right nominal capacitance by checking capacitor's DC bias characteristics. In this example, GRM188R60J106ME84D, which is a 10-µF ceramic capacitor with high effective capacitance value at DC biased condition, is selected for V_OUT rail. Two 10-μF capacitors in parallel are recommended to get the desired effective capacitance.