ZHCSLA4E May 2020 – October 2024 TPS61378-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Device Comparison Table
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 VCC Power Supply
- 7.3.2 Input Undervoltage Lockout (UVLO)
- 7.3.3 Enable and Soft Start
- 7.3.4 Shut Down
- 7.3.5 Switching Frequency Setting
- 7.3.6 Spread Spectrum Frequency Modulation
- 7.3.7 Adjustable Peak Current Limit
- 7.3.8 Bootstrap
- 7.3.9 Load Disconnect
- 7.3.10 MODE/SYNC Configuration
- 7.3.11 Overvoltage Protection (OVP)
- 7.3.12 Output Short Protection/Hiccup
- 7.3.13 Power-Good Indicator
- 7.3.14 Thermal Shutdown
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2 Detailed Design Procedure
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Revision History
- 13Mechanical, Packaging, and Orderable Information
7.4.4 Down Mode
The TPS61378-Q1 features down mode operation when input voltage is close to or higher than output voltage. In down mode, output voltage is regulated at target value, even when VIN > VO. The TPS61378-Q1 high-side and low-side FETs are switching devices that always work in boost operation, where the isolation FET always works as a linear device.
For boost circuits, on-time or duty cycle is reduced as input voltage approaches output voltage. The TPS61378-Q1 enters down mode when VIN reaches 85% (typical) of VO voltage at 2.2 MHz. Exiting down mode requires VIN to be reduced below 85% (typical) of VO voltage at 2.2 MHz.
In normal operation, the isolation FET is fully on.
When down mode is triggered and VIN is less than VO pin voltage, the OUT pin has a fixed 2 V (typical) above VO pin voltage. An isolation FET works in LDO mode to regulate VO pin voltage with a 2-V constant voltage drop.
When down mode is triggered and VIN is 100 mV (typical) higher than VO pin voltage, the OUT pin has an approximated 3 V (typical) above the VIN pin voltage. As VIN keeps rising, the OUT pin continues rising with 3 V on top of VIN. In addition, an isolation FET works in LDO mode to regulate VO pin voltage with a voltage differential of the OUT pin and VO pin.
Refer to Figure 7-1.
Figure 7-1 Down ModeTake care during short-to-ground condition when operation VIN is above 6 V. During hiccup on, the device operates in down mode and the isolation FET voltage drop is VIN + 3 V (OUT pin to VO pin).