ZHCSJN0B April 2019 – October 2019 TPS61390
PRODUCTION DATA.
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| VSP | 1 | O | Sample/Hold voltage output with single-ended output. | |
| GAIN | 2 | I | GAIN of the current mirror selection indicator of the sample/hold output: | |
| Output low: sample/hold for current mirror gain 4 : 5; | ||||
| Output high: sample/hold for current mirror gain 1 : 5; | ||||
| This pin can also be any input pin: | ||||
| Input low: sample/hold for current mirror gain 4 : 5; | ||||
| Input high: sample/hold for current mirror gain 1 : 5 | ||||
| MON2 | 3 | O | Current mirror output pin of 1 : 5 ratio (Mirror current: APD current) | |
| MON1 | 4 | O | Current mirror output pin of 4 : 5 ratio (Mirror current: APD current) | |
| APD | 5 | O | Power supply for the APD, connect this pin with the cathode of APD | |
| MONIN | 6 | I | Current mirror input pin | |
| GND | 7 | – | Power Ground | |
| SW | 8 | PWR | The switching node pin of the converter. It is connected to the drain of the internal low-side power MOSFET and the source of the internal high-side power MOSFET | |
| CAP | 9 | O | Connecting a capacitor externally to lower the noise for current mirror. | |
| VIN | 10 | I | IC power supply input | |
| ISHORT | 11 | O | Programming the current limit for high optical power protection by a resistor between this pin and GND. | |
| FB | 12 | I | Feedback voltage | |
| EN | 13 | I | Enable logic input. Logic high level enables the device. Logic low level disables the device and turns it into shutdown mode | |
| SAMPLE | 14 | I | The sample trigger pin, the rising edge of this pin to trigger the sample and falling edge to hold the sampled voltage. | |
| AVCC | 15 | I | Power supply for the sample/hold circuitry | |
| AGND | 16 | – | Analog ground for the sample / hold and current mirror circuitry | |
| Exposed Thermal Pad | Connect with GND, TI recommends connecting to Power GND on PCB | |||