ZHCSHS6F November 2017 – November 2024
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
The device has a power-good output. The PG pin goes high impedance after the FB pin voltage is above 96% and less than 105% of the nominal voltage, and is driven low after the voltage falls below typically 92% or higher than 110% of the nominal voltage. The PG pin is an open-drain output and is specified to sink up to 1 mA. The power-good output requires a pullup resistor connecting to any voltage rail less than 5.5 V.
The PG signal can be used for sequencing of multiple rails by connecting the PG signal to the EN pin of other converters. Leave the PG pin unconnected when not used. The PG rising edge has a 100-µs blanking time and the PG falling edge has a deglitch delay of 20 µs.
DEVICE CONDITIONS | LOGIC STATUS | ||
---|---|---|---|
HIGH IMPEDANCE | LOW | ||
Enable | EN = HIGH, VFB ≥ 0.576 V | √ | |
EN = HIGH, VFB ≤ 0.552 V | √ | ||
EN = HIGH, VFB ≤ 0.63 V | √ | ||
EN = HIGH, VFB ≥ 0.66 V | √ | ||
Shutdown | EN = LOW | √ | |
Thermal shutdown | TJ > TJSD | √ | |
UVLO | 0.7 V < VIN < VUVLO | √ | |
Power supply removal | VIN < 0.7 V | undefined |