ZHCSHZ8B april 2018 – february 2023 TPS62147 , TPS62148
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SUPPLY | |||||||
IQ | Operating Quiescent Current | EN = high, IOUT= 0 mA, Device not switching, TJ= 85 °C | 35 | µA | |||
IQ | Operating Quiescent Current | EN = high, IOUT= 0 mA, Device not switching | 18 | 46 | µA | ||
ISD | Shutdown Current | EN = 0 V, Nominal value at TJ= 25 °C, Max value at TJ= 85 °C | 1 | 8 | µA | ||
VUVLO | Undervoltage Lockout Threshold | Rising Input Voltage | 2.8 | 2.9 | 3.0 | V | |
Falling Input Voltage | 2.5 | 2.6 | 2.7 | V | |||
TSD | Thermal Shutdown Temperature | Rising Junction Temperature | 160 | °C | |||
Thermal Shutdown Hysteresis | 20 | ||||||
CONTROL (EN, SS/TR, PG, MODE, FSEL) | |||||||
VIH | High Level Input Voltage for FSEL, MODE pin | 0.9 | V | ||||
VIL | Low Level Input Voltage for FSEL, MODE pin | 0.3 | V | ||||
VIH | Input Threshold Voltage for EN pin; rising edge | 0.77 | 0.8 | 0.83 | V | ||
VIL | Input Threshold Voltage for EN pin; falling edge | 0.67 | 0.7 | 0.73 | V | ||
ILKG_EN | Input Leakage Current for EN, FSEL, MODE | VIH = VIN or VIL= GND | 100 | nA | |||
VTH_PG | Power Good Threshold Voltage; dc level | Rising (%VOUT) | 93% | 96% | 98% | ||
Hysteresis | Falling (%VOUT) | 3% | 4.5% | ||||
VOL_PG | Power Good Output Low Voltage | IPG = -2 mA | 0.07 | 0.3 | V | ||
ILKG_PG | Input Leakage Current (PG) | VPG = 5 V | 100 | nA | |||
ISS/TR | SS/TR pin source current | 2.5 | µA | ||||
ISS/TR tolerance | TJ= –40 °C to +125 °C | ±0.2 | µA | ||||
Tracking gain | VFB / VSS/TR | 1 | |||||
Tracking offset | feedback voltage with VSS/TR = 0 V | 11 | mV | ||||
POWER SWITCH | |||||||
RDS(ON) | High-Side MOSFET ON-Resistance | VIN ≥ 4 V | 100 | 180 | mΩ | ||
Low-Side MOSFET ON-Resistance | VIN ≥ 4 V | 39 | 67 | mΩ | |||
ILIMH | High-Side MOSFET Current Limit | dc value(2) | 2.8 | 3.5 | 4.2 | A | |
ILIML | Low-Side MOSFET Current Limit | dc value(2) | 2.8 | 3.5 | 4.2 | A | |
ILIMNEG | Negative current limit; average value | dc value | 1.5 | A | |||
OUTPUT | |||||||
VFB | Feedback Voltage | 0.7 | V | ||||
ILKG_FB | Input Leakage Current (FB) | VFB= 0.7 V | 1 | 70 | nA | ||
VFB | Feedback Voltage Accuracy(1) | VIN ≥ VOUT +1 V | PWM mode | -1% | 1% | ||
VIN ≥ VOUT +1 V; VOUT ≥ 1.5 V | PFM mode; Co,eff ≥ 47 µF, L = 1 µH for FSEL = high, L = 1.5 µH for FSEL = low | -1% | 2% | ||||
1 V ≤ VOUT < 1.5 V | PFM mode; Co,eff ≥ 47 µF, L = 1 µH for FSEL = high, Co,eff ≥ 60 µF, L = 1.5 µH for FSEL = low | -1% | 2.5% | ||||
VOUT < 1 V | PFM mode; Co,eff ≥ 75 µF, L = 1 µH for FSEL = high, L = 1.5 µH for FSEL = low | -1% | 2.5% | ||||
VFB | Feedback Voltage Accuracy with Voltage Tracking | VIN ≥ VOUT +1 V; VSS/TR = 0.35 V | PWM mode | -2% | 7.5% | ||
Load Regulation | PWM mode operation | 0.05 | %/A | ||||
Line Regulation | PWM mode operation, IOUT= 1 A, VIN ≥ Vout + 1 V or VIN ≥ 3.5 V whichever is larger | 0.02 | %/V | ||||
Output Discharge Resistance | 100 | Ω | |||||
tdelay | Start-up Delay time | IO= 0 mA, Time from EN=high to start switching; VIN applied already | 200 | 300 | µs | ||
tramp | Ramp time; SS/TR pin open | IO= 0 mA, Time from first switching pulse until 95% of nominal output voltage; device not in current limit | 150 | µs |