10.1 Layout Guidelines

• A proper layout is critical for the operation of a switched-mode power supply, even more at high switching frequencies. Therefore, the PCB layout of the TPS62152-Q1 device demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity.
• See Figure 37 for the recommended layout of the TPS62152-Q1 device, which is designed for common external ground connections. Therefore, both AGND and PGND pins connect directly to the exposed thermal pad. On the PCB, the direct common ground connection of AGND and PGND to the exposed thermal pad and the system ground (ground plane) is mandatory.
• Provide low-inductive, low-resistive paths for loops with high di/dt. Paths conducting the switched load current should be as short and wide as possible.
• Provide low-capacitive paths (with respect to all other nodes) for wires with high dv/dt.
• Place the input and output capacitance as close as possible to the IC pins and provide short connections between C_IN to GND and C_OUT to GND.
• Avoid parallel wiring over long distances as well as narrow traces.
• Use loops that conduct an alternating current to outline an area as small as possible because the energy radiated is proportional to this area.
• VOS must be connected with a short trace and must be adequate distance from high dv/dt signals (for example, SW). Because this node caries information about the output voltage, it should have connections as close as possible to the actual output voltage (at the output capacitor).
• Because this device has fixed output voltage, TI recommends connecting the FB pin to GND with a short trace.
• Keep the capacitor on the SS/TR pin and on AVIN close to the device. Connect these pins directly to the system ground plane.
• Solder the exposed thermal pad to the circuit board for mechanical reliability and to achieve appropriate power dissipation.
• The recommended layout is implemented on the EVM and shown in TPS62130EVM-505, TPS62140EVM-505, and TPS62150EVM-505 Evaluation Modules, SLVU437. Additionally, the EVM Gerber data is available for download in the zipped file: SLVC394 from the device product folder, www.ti.com/product/TPS62152-Q1.

10.2 Layout Example

Figure 37. Layout Example

10.3 Thermal Considerations

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are:

• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB by soldering the exposed thermal pad
• Introducing airflow in the system

For more details on how to use the thermal parameters, see Thermal Characteristics of Linear and Logic Packages Using JEDEC PCB Designs, SZZA017, and Semiconductor and IC Package Thermal Metrics, SPRA953.

The design of the TPS62152-Q1 device is for a maximum operating junction temperature (T_J) of 125°C. Therefore, the power losses that can be dissipated over the actual thermal resistance impose a limit on the maximum output power, given the package and the surrounding PCB structures. If the thermal resistance of the package is given, the increasing the size of the surrounding copper area and making a proper thermal connection of the IC can reduce the thermal resistance. A recommendation for getting improved thermal behavior is to use top layer metal to connect the device with wide and thick metal lines. Internal ground layers can connect to vias directly under the IC for improved thermal performance.

If short circuit or overload conditions are present, the device is protected by limiting internal power dissipation.