Proper layout is critical for the operation of a switched-mode power supply, even more at high switching frequencies. Therefore, the PCB layout of the TPS6215x device demands careful attention to ensure operation and to get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability and accuracy weaknesses, increased EMI radiation, and noise sensitivity.

See Figure 11-1 for the recommended layout of the TPS6215x device, which is designed for common external ground connections. Both AGND (pin 6) and PGND (pins 15 and 16) are directly connected to the exposed thermal pad. On the PCB, the direct common-ground connection of AGND and PGND to the exposed thermal pad and the system ground (ground plane) is mandatory. Also, connect VOS (pin 14) in the shortest way to V_OUT at the output capacitor. To avoid noise coupling into the VOS line, this connection should be separated from the V_OUT power line and plane as shown in Section 11.2.

Provide low-inductance and -resistance paths for loops with high di/dt. Paths conducting the switched load current should be as short and wide as possible. Provide low-capacitance paths (with respect to all other nodes) for wires with high dv/dt. The input and output capacitance should be placed as close as possible to the IC pins, and parallel wiring over long distances as well as narrow traces should be avoided. Loops which conduct an alternating current should outline an area as small as possible, as this area is proportional to the energy radiated.

Sensitive nodes like FB (pin 5) and VOS (pin 14) must be connected with short wires and not near high dv/dt signals [for example, SW (pins 1, 2, and 3)]. As FB and VOS pins carry information about the output voltage, they should be connected as closely as possible to the actual output voltage (at the output capacitor). The capacitor on SS/TR (pin 9) and on AVIN (pin 19), as well as the FB resistors, R1 and R2, should be kept close to the IC and connect directly to those pins and the system ground plane.

The exposed thermal pad must be soldered to the circuit board for mechanical reliability and to achieve adequate power dissipation.

The recommended layout is implemented on the EVM and shown in its Users Guide, SLVU437. Additionally, the EVM Gerber data are available for download here, SLVC394.