11.1.1 PCB Layout

A recommended PCB layout for the TPS62180 dual phase solution is shown below. It ensures best electrical and optimized thermal performance considering the following important topics:

• The input capacitors must be placed as close as possible to the appropriate pins of the device. This provides low resistive and inductive paths for the high di/dt input current. The input capacitance is split, as is the V_IN connection, to avoid interference between the input lines.
• The SW node connection from the IC to the inductor conducts high currents. It should be kept short and can be designed in parallel with an internal or bottom layer plane, to provide low resistance and enhanced thermal behavior.
• The V_OUT regulation loop is closed with C_OUT and its ground connection. If a ground layer or plane is used, a direct connection by vias, as shown, is recommended. Otherwise the connection of C_OUT to GND must be short for good load regulation.
• The FB node is sensitive to dv/dt signals. Therefore the resistive divider should be placed close to the FB pin, avoiding long trace distance. Using the TPS62182 (fixed output voltage version), the FB pin can be left floating, but it is good practice and recommended to connect it to AGND for best thermal characteristics.