The bit detection is based on a PWM scheme, where the criterion is the relation between the low time and high time of the low or high bit (t_{L_xB} and t_{H_xB}). Bit detection can be simplified to:

High bit: t_{H_HB} > t_{L_HB}, but with t_{H_HB} at least 2× t_{L_HB}, see Figure 8-3.

Low bit: t_{L_LB} > t_{H_LB}, but with t_{L_LB} at least 2× t_{H_LB}, see Figure 8-3.

The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge. Detection of a 0 or 1 depends on the relation between t_{L_xB} and t_{H_xB}.