SLVS676D JUNE   2006  – July 2015 TPS62420 , TPS62421

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Dissipation Ratings
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
      1. 8.1.1 Converter 1
      2. 8.1.2 Converter 2
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Dynamic Voltage Positioning
      2. 8.3.2 Undervoltage Lockout
      3. 8.3.3 Mode Selection
      4. 8.3.4 Enable
      5. 8.3.5 DEF_1 Pin Function
      6. 8.3.6 180° Out-of-Phase Operation
      7. 8.3.7 Thermal Shutdown
      8. 8.3.8 Short Circuit Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Soft-Start
      2. 8.4.2 100% Duty Cycle Low Dropout Operation
      3. 8.4.3 Power-Save Mode
    5. 8.5 Programming
      1. 8.5.1 EasyScale™ Interface: One-Pin Serial Interface for Dynamic Output Voltage Adjustment
        1. 8.5.1.1 General
        2. 8.5.1.2 Protocol
        3. 8.5.1.3 Bit Decoding
        4. 8.5.1.4 Acknowledge
        5. 8.5.1.5 MODE Selection
    6. 8.6 Register Maps
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Output Voltage Setting
        1. 9.1.1.1 Converter 1 Adjustable Default Output Voltage Setting
        2. 9.1.1.2 Converter 2
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application Circuit 1.5-V and 2.85-V Adjustable Outputs
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Output Filter Design (Inductor and Output Capacitor)
            1. 9.2.1.2.1.1 Inductor Selection
            2. 9.2.1.2.1.2 Output Capacitor Selection
            3. 9.2.1.2.1.3 Input Capacitor Selection
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Typical Application Circuit TPS62421
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage on VIN(2) –0.3 7 V
Voltage on EN, MODE/DATA, DEF_1 –0.3 VIN +0.3, ≤7 V
Maximum current into MODE/DATA 500 μA
Voltage on SW1, SW2 –0.3 7 V
Voltage on ADJ2, FB1 –0.3 VIN +0.3, ≤7 V
TJ(max) Maximum junction temperature 150 °C
TA Operating ambient temperature –40 85 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN Supply voltage 2.5 6 V
Output voltage range for adjustable voltage 0.6 VIN V
TA Operating ambient temperature –40 85 °C
TJ Operating junction temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC(1) TPS62420, TPS62421 UNIT
DRC (VSON)
10 PINS
RθJA Junction-to-ambient thermal resistance 45.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 64.3 °C/W
RθJB Junction-to-board thermal resistance 20.4 °C/W
ψJT Junction-to-top characterization parameter 1.3 °C/W
ψJB Junction-to-board characterization parameter 20.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.8 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

VIN = 3.6 V, VOUT = 1.8 V, EN = VIN, MODE = GND, L = 2.2 μH, COUT = 20 μF, TA = –40°C to 85°C typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN Input voltage range 2.5 6 V
IQ Operating quiescent current One converter, IOUT = 0 mA. PFM mode enabled (Mode = 0) device not switching,
EN1 = 1 or EN2 = 1		 19 29 μA
Two converter, IOUT = 0 mA. PFM mode enabled (Mode = 0) device not switching,
EN1 = 1 and EN2 = 1		 32 48 μA
IOUT = 0 mA, MODE/DATA = GND, for one converter, VOUT 1.575 V(1) 23 μA
IOUT = 0 mA, MODE/DATA = VIN, for one converter, VOUT 1.575 V(1) 3.6 mA
ISD Shutdown current EN1, EN2 = GND, VIN = 3.6 V(2) 1.2 3 μA
EN1, EN2 = GND, VIN ramped from 0 V to 3.6 V(3) 0.1 1
VUVLO Undervoltage lockout threshold Falling 1.5 2.35 V
Rising 2.4
ENABLE EN1, EN2
VIH High-level input voltage, EN1, EN2 1.2 VIN V
VIL Low-level input voltage, EN1, EN2 0 0.4 V
IIN Input bias current, EN1, EN2 EN1, EN2 = GND or VIN 0.05 1.0 μA
DEF_1 INPUT
VDEF_1H DEF_1 high level input voltage DEF_1 pin is a digital input at fixed output voltage options (TPS62421) 0.9 VIN V
VDEF_1L DEF_1 low level input voltage 0 0.4
IIN Input biasd current DEF_1 DEF_1 = GND or VIN 0.01 1 μA
MODE/DATA
VIH High-level input voltage, MODE/DATA 1.2 VIN V
VIL Low-level input voltage, MODE/DATA 0 0.4 V
IIN Input bias current, MODE/DATA MODE/DATA = GND or VIN 0.01 1 μA
VOH Acknowledge output voltage high Open-drain, through external pullup resistor VIN V
VOL Acknowledge output voltage low Open-drain, sink current 500 μA 0 0.4 V
INTERFACE TIMING
tStart Start time 2 μs
tH_LB High time low bit, logic 0 detection Signal level on MODE/DATA pin is > 1.2 V 2 200 μs
tL_LB Low time low bit, logic 0 detection Signal level on MODE/DATA pin < 0.4 V 2x tH_LB 400 μs
tL_HB Low time high bit, logic 1 detection Signal level on MODE/DATA pin < 0.4 V 2 200 μs
tH_LB High time high bit, logic 1 detection Signal level on MODE/DATA pin is > 1.2 V 2x tL_HS 400 μs
TEOS End of Stream TEOS 2 μs
tACKN Duration of acknowledge condition (MODE/DATE line pulled low by the device) VIN 2.5 V to 6 V 400 520 μs
tvalACK Acknowledge valid time 2 μs
ttimeout Time-out for entering power-save mode MODE/DATA pin changes from high to low 520 μs
POWER SWITCH
RDS(ON) P-channel MOSFET on-resistance, converter 1, 2 VIN = VGS = 3.6 V 280 620 mΩ
ILK_PMOS P-channel leakage current VDS = 6 V 1 μA
RDS(ON) N-channel MOSFET on-resistance converter 1, 2 VIN = VGS = 3.6 V 200 450 mΩ
ILK_SW1/SW2 Leakage current into SW1/SW2 pin Includes N-Chanel leakage current,
VIN = open, VSW = 6 V, EN = GND(4)		 6 7.5 μA
ILIMF Forward current limit PMOS and NMOS OUT1 600 mA 2.5 V ≤ VIN ≤ 6 V 0.85 1.0 1.15 A
OUT2 1000 mA 1.19 1.4 1.61
TSD Thermal shutdown Increasing junction temperature 150 °C
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
OSCILLATOR
fSW Oscillator frequency 2.5 V ≤ VIN ≤ 6 V 2.0 2.25 2.5 MHz
OUTPUT
VOUT Adjustable output voltage range 0.6 VIN V
Vref Reference voltage 600 mV
VOUT (PFM) DC output voltage accuracy PFM mode, adjustable and fixed output voltage(6) Voltage positioning active,
MODE/DATA = GND, device operating in PFM mode, VIN = 2.5 V to 5 V (5)(7)		 –1.5% 1.01 × VOUT 2.5%
VOUT MODE/DATA = GND; device operating in PWM mode VIN = 2.5 V to 6 V(7) –1% 0% 1%
VIN = 2.5 V to 6 V, Mode/Data = VIN , Fixed PWM operation, 0 mA < IOUT < IOUTMAX(8) –1% 0% 1%
DC output voltage load regulation PWM operation mode 0.5 %/A
tStart up Start-up time Activation time to start switching(9) 170 μs
tRamp VOUT Ramp UP time Time to ramp from 5% to 95% of VOUT 750 μs
(1) Device is switching with no load on the output, L = 3.3 μH, value includes losses of the coil
(2) These values are valid after the device has been already enabled one time (EN1 or EN2 = High) and supply voltage VIN has not powered down.
(3) After the first enable, these values are valid when the device is disabled (EN1 and EN2 = Low) and supply voltage VIN is powered up. The values remain valid until the device has been enabled first time (EN1 or EN2 = high).
(4) At pins SW1 and SW2 an internal resistor of 1 MΩ is connected to GND
(5) Configuration L typ 2.2 μH, COUT typical 20 μF, see parameter measurement information, the output voltage ripple depends on the effective capacitance of the output capacitor, larger output capacitors lead to tighter output voltage tolerance
(6) Output voltage specification does not include tolerance of external voltage programming resistors
(7) In power-save mode, PWM operation is typically entered at IPSM = VIN/32 Ω.
(8) For VOUT > 2.2 V, VIN min = VOUT +0.3 V
(9) This time is valid if one converter turns from shutdown mode (EN2 = 0) to active mode (EN2 =1) and the other converter is already enabled (that is, EN1 = 1). In case both converters are turned from shutdown mode (EN1 and EN2 = Low) to active mode (EN1 and/or EN2 = 1) a value of typical 80 μs for ramp up of internal circuits needs to be added. After tStart the converter starts switching and ramps VOUT.

7.6 Dissipation Ratings

PACKAGE RθJA POWER RATING FOR TA ≤ 25°C DERATING FACTOR ABOVE TA = 25°C
DRC 49°C/W 2050 mW 21 mW/°C

7.7 Typical Characteristics

TPS62420 TPS62421 fosc_vi_las676.gifFigure 1. FOSC vs VIN
TPS62420 TPS62421 idd2_vi_las676.gifFigure 3. Iq For Both Converters, Not Switching
TPS62420 TPS62421 rdson2_vi_las276.gifFigure 5. RDSON NMOS vs VIN
TPS62420 TPS62421 idd_vi_las676.gifFigure 2. Iq For One Converter, Not Switching
TPS62420 TPS62421 rdson_vi_las676.gifFigure 4. RDSON PMOS vs VIN
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