ZHCSHZ2E December 2014 – March 2022 TPS62406-Q1 , TPS62407-Q1 , TPS62422-Q1 , TPS62423-Q1 , TPS62424-Q1
PRODUCTION DATA
The TPS624xx-Q1 device includes two synchronous step-down converters. The converters operate with typically 2.25-MHz fixed-frequency pulse-width modulation (PWM) at moderate to heavy load currents. With the power-save mode enabled, the converters automatically enter power-save mode at light load currents and operate in PFM (pulse frequency modulation).
During PWM operation, the converters use a unique fast-response voltage-mode controller scheme with input-voltage feed-forward to achieve good line and load regulation, allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch turns on and the inductor current ramps up until the comparator trips and the control logic turns off the switch.
Each converter integrates two current limits, one in the P-channel MOSFET and another one in the N-channel MOSFET. When the current in the P-channel MOSFET reaches its current limit, the P-channel MOSFET turns off and the N-channel MOSFET turns on. If the current in the N-channel MOSFET is above the N-MOS current limit threshold, the N-channel MOSFET remains on until the current drops below its current limit.
The two DC-DC converters operate synchronized to each other. A 180° phase shift between converter 1 and converter 2 decreases the input rms current.