SLVS897C January   2009  – December 2015 TPS62590

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Dynamic Voltage Positioning
      2. 7.3.2 Undervoltage Lockout
      3. 7.3.3 Mode Selection
      4. 7.3.4 Enable
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Soft-Start
      2. 7.4.2 Power-Save Mode
      3. 7.4.3 100% Duty Cycle Low Dropout Operation
      4. 7.4.4 Short-Circuit Protection
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Voltage Setting
        2. 8.2.2.2 Output Filter Design (Inductor and Output Capacitor)
          1. 8.2.2.2.1 Inductor Selection
          2. 8.2.2.2.2 Output Capacitor Selection
          3. 8.2.2.2.3 Input Capacitor Selection
      3. 8.2.3 Application Curves
    3. 8.3 System Example
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN Input voltage(2) –0.3 7 V
Voltage at EN, MODE –0.3 VIN + 0.3, ≤ 7
Voltage on SW –0.3 7
Peak output current Internally limited A
TJ Maximum operating junction temperature –40 125 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VIN Supply voltage 2.5 5.5 V
Output voltage for adjustable voltage 0.75 VIN V
TA Operating ambient temperature –40 85 °C
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS62590 UNIT
DRV (WSON)
6 PINS
RθJA Junction-to-ambient thermal resistance 67.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 88.5 °C/W
RθJB Junction-to-board thermal resistance 37.2 °C/W
ψJT Junction-to-top characterization parameter 2.0 °C/W
ψJB Junction-to-board characterization parameter 37.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 7.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for condition VIN = EN = 3.6 V. External components CIN = 10 μF 0603, COUT = 10 μF 0603, L = 2.2 μH, refer to parameter measurement information.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
VIN Input voltage range 2.5 5.5 V
IOUT Output current VIN 2.7 V to 5.5 V 1000 mA
VIN 2.5 V to 2.7 V 600
IQ Operating quiescent current IOUT = 0 mA, PFM mode enabled
(MODE = GND) device not switching, see (1)
15 μA
IOUT = 0 mA, switching with no load
(MODE = VIN) PWM operation,
VOUT = 1.8 V, VIN = 3 V
3.8 mA
ISD Shutdown current EN = GND 0.5 μA
UVLO Undervoltage lockout threshold Falling 1.85 V
Rising 1.95
ENABLE, MODE
VIH High level input voltage, EN, MODE 2.5 V ≤ VIN ≤ 5.5 V 1 VIN V
VIL Low level input voltage, EN, MODE 2.5 V ≤ VIN ≤ 5.5 V 0 0.4 V
IIN Input bias current, EN, MODE EN, MODE = GND or VIN 0.01 1 μA
POWER SWITCH
RDS(on) High side MOSFET on-resistance VIN = VGS = 3.6 V, TA = 25°C 250
Low side MOSFET on-resistance 190
ILIMF Forward current limit MOSFET high side and low side VIN = VGS = 3.6 V 1.19 1.4 1.68 A
TSD Thermal shutdown Increasing junction temperature 140 °C
Thermal shutdown hysteresis Decreasing junction temperature 20
OSCILLATOR
fSW Oscillator frequency 2.5 V ≤ VIN  ≤ 5.5 V 2.25 MHz
OUTPUT
VO Adjustable output voltage range 0.75 VI V
VREF Reference voltage 600 mV
VFB(PWM) Feedback voltage MODE = VIN, PWM operation,
2.5 V ≤ VIN  ≤ 5.5 V, see (2)
–2.5% 0% 2.5%
VFB(PFM) Feedback voltage PFM mode MODE = GND, device in PFM mode, +1% voltage positioning active, see (1) 1%
Load regulation –1 %/A
tStart Up Start-up time Time from active EN to reach 95% of VOUT 500 μs
tRamp VOUT ramp-up time Time to ramp from 5% to 95% of VOUT 250 μs
Ilkg Leakage current into SW pin VIN = 3.6 V, VIN = VOUT = VSW, EN = GND,
see (3)
0.1 1 μA
(1) In PFM mode, the internal reference voltage is set to typical 1.01 × VREF . See the parameter measurement information.
(2) For VIN = VOUT + 1 V.
(3) In fixed output voltage versions, the internal resistor divider network is disconnected from FB pin.

6.6 Typical Characteristics

TPS62590 isd_v_vin_lvs897.gif Figure 1. Shutdown Current onto VIN vs Input Voltage
TPS62590 rds_hs_vin_lvs897.gif Figure 3. Static Drain-Source ON-State Resistance
vs Input Voltage
TPS62590 iq_v_vin_lvs897.gif Figure 2. Quiescent Current vs Input Voltage
TPS62590 rds_ls_vin_lvs897.gif Figure 4. Static Drain-Source ON-State Resistance
vs Input Voltage