ZHCSNV7A March   2020  – December 2021 TPS62816-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Precise Enable
      2. 9.3.2 COMP/FSET
      3. 9.3.3 MODE/SYNC
      4. 9.3.4 Spread Spectrum Clocking (SSC)
      5. 9.3.5 Undervoltage Lockout (UVLO)
      6. 9.3.6 Power Good Output (PG)
      7. 9.3.7 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Pulse Width Modulation (PWM) Operation
      2. 9.4.2 Power Save Mode Operation (PWM/PFM)
      3. 9.4.3 100% Duty-Cycle Operation
      4. 9.4.4 Current Limit and Short Circuit Protection
      5. 9.4.5 Foldback Current Limit and Short Circuit Protection
      6. 9.4.6 Output Discharge
      7. 9.4.7 Soft Start/Tracking (SS/TR)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Programming the Output Voltage
      2. 10.1.2 External Component Selection
        1. 10.1.2.1 Inductor Selection
        2. 10.1.2.2 Capacitor Selection
          1. 10.1.2.2.1 Input Capacitor
          2. 10.1.2.2.2 Output Capacitor
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
    3. 10.3 System Examples
      1. 10.3.1 Voltage Tracking
      2. 10.3.2 Synchronizing to an External Clock
      3. 10.3.3 Compensation Settings
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 接收文档更新通知
    4. 13.4 支持资源
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 术语表
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

Over operating junction temperature range (TJ = –40°C to +150°C) and VIN = 2.7 V to 6 V. Typical values at VIN = 5 V and TJ = 25°C. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY
IQ Quiescent current EN = VIN, no load, device not switching, TJ = 125°C, MODE = GND 36 μA
IQ Quiescent current EN = VIN, no load, device not switching, MODE = GND, VOUT = 0.6 V 26 50 μA
ISD Shutdown current EN = GND,  at TJ = 125°C 90 μA
ISD Shutdown current EN = GND, nominal value at TJ = 25°C, max value at TJ = 150°C 2.2 230 μA
VUVLO Undervoltage lockout threshold VIN rising 2.45 2.6 2.7 V
VIN falling 2.1 2.5 2.6 V
TJSD Thermal shutdown threshold TJ rising 180 °C
Thermal shutdown hysteresis TJ falling 15 °C
CONTROL and INTERFACE
VIH,EN Input threshold voltage at EN, rising edge 1.05 1.1 1.15 V
VIL,EN Input threshold voltage at EN, falling edge 0.96 1.0 1.05 V
VIH High-level input-threshold voltage at MODE/SYNC 1.1 V
IIH,EN Input leakage current into EN VIH = VIN or VIL = GND 125 nA
VIL Low-level input-threshold voltage at MODE/SYNC 0.3 V
IIH Input leakage current into MODE/SYNC 250 nA
tDelay Enable delay time Time from EN high to device starts switching; VIN applied already 135 270 520 µs
tRamp Output voltage ramp time, SS/TR pin open IOUT = 0 mA, time from device starts switching to power good; device not in current limit 90 150 220 µs
ISS/TR SS/TR source current 8 10 12 µA
RDIS Internal discharge resistance on SS/TR when EN = low 0.7 1.1 1.5 kΩ
Tracking gain VFB / VSS/TR 1
Tracking offset VFB when VSS/TR = 0 V ±1 mV
fSYNC Frequency range on MODE/SYNC pin for synchronization 1.8 4 MHz
Duty cycle of synchronization signal at MODE/SYNC 20 80 %
Time to lock to external frequency 50 µs
resistance from COMP/FSET to GND for logic low Internal frequency setting with f = 2.25 MHz 0 2.5 kΩ
Voltage on COMP/FSET for logic high internal frequency setting with f = 2.25 MHz VIN V
VTH_PG UVP power good threshold voltage; dc level rising (%VFB) 92% 95% 98%
VTH_PG UVP power good threshold voltage; dc level falling (%VFB) 87% 90% 93%
VTH_PG OVP power good threshold voltage; dc level rising (%VFB) 107% 110% 113%
OVP power good threshold voltage; dc level falling (%VFB) 104% 107% 111%
VOL,PG Low-level output voltage at PG ISINK_PG = 2 mA 0.01 0.3 V
IIH,PG Input leakage current into PG VPG = 5 V 100 nA
tPG PG deglitch time For a high level to low level transition on the power good output 40 µs
OUTPUT
VFB Feedback voltage 0.6 V
IIH,FB Input leakage current into FB VFB = 0.6 V 1 70 nA
VFB Feedback voltage accuracy PWM, VIN ≥ VOUT + 1 V –1% 1%
VFB Feedback voltage accuracy PFM, VIN ≥ VOUT + 1 V, VOUT ≥ 1.5 V, Co,eff ≥ 47 µF –1% 2%
VFB Feedback voltage accuracy PFM, VIN ≥ VOUT + 1 V, VOUT < 1.5 V, Co,eff ≥ 68 µF
 		 –1% 2.5%
VFB Feedback voltage accuracy with voltage tracking VIN ≥ VOUT + 1 V, VSS/TR = 0.3 V, PWM mode –5% 5%
Load regulation PWM 0.05 %/A
Line regulation PWM, IOUT = 1 A, VIN ≥ VOUT + 1 V 0.02 %/V
RDIS Output discharge resistance 50 Ω
fSW PWM switching frequency range MODE = high, see the FSET pin functionality about setting the switching frequency 1.8 2.25 4 MHz
fSW PWM switching frequency With COMP/FSET tied to GND or VIN 2.08 2.25 2.4 MHz
fSW PWM switching frequency tolerance using a resistor from COMP/FSET to GND –12% 12%
ton,min Minimum on time of high-side FET VIN ≥ 3.3 V, TJ = –40°C to 125°C 45 67 ns
ton,min Minimum on time of low-side FET 15 ns
RDS(ON) High-side FET on-resistance VIN ≥ 5 V
 		 11 26 mΩ
Low-side FET on-resistance VIN ≥ 5 V 9 19 mΩ
IIH High-side MOSFET leakage current 0.01 230 µA
IIH Low-side MOSFET leakage current V(SW) = 6 V 0.01 290 µA
IIH SW leakage V(SW) = 0.6V, current into SW pin -0.05 30 µA
ILIMH High-side FET switch current limit DC value, VIN = 3 V to 6 V 7.3 9.2 10.4 A
ILIMNEG Low-side FET negative current limit DC value -3 A
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