11.1 Layout Guidelines

The recommended PCB layout for the TPS6282x is shown below. It ensures best electrical and optimized thermal performance considering the following important topics:

- The input capacitor(s) must be placed as close as possible to the VIN and PGND pins of the device. This provides low resistive and inductive paths for the high di/dt input current.

- The SW node connection from the IC to the inductor conducts alternating high currents. It should be kept short.

- The V_OUT regulation loop is closed with COUT and its ground connection. To avoid load regulation and EMI noise, the loop should be kept short.

- The FB node is sensitive to dv/dt signals. Therefore the resistive divider should be placed close to the FB and AGND pins.

For more detailed information about the actual EVM solution, see the EVM users guide.