ZHCSNO6B February 2023 – March 2024 TPS628301 , TPS628302 , TPS628303 , TPS628304
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Device Options
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
7.4.3 Power Good
The TPS62830x has a built-in power-good (PG) function. The PG pin goes high impedance when the output voltage has reached the nominal value. Otherwise, including when disabled, in UVLO or in thermal shutdown, PG is Low (see Table 7-1). The PG function is formed with a window comparator, which has an upper and lower voltage threshold. The PG pin is an open-drain output and is specified to sink up to 1 mA. The power-good output requires a pullup resistor connecting to any voltage rail less than 5.5 V.
| DEVICE CONDITIONS | LOGIC STATUS | ||
|---|---|---|---|
| HIGH Z | LOW | ||
| Enable | EN = High, VFB ≥ 0.48 V | √ | |
| EN = High, VFB ≤ 0.56 V | √ | ||
| EN = High, VFB ≤ 0.525 V | √ | ||
| EN = High, VFB ≥ 0.55 V | √ | ||
| Shutdown | EN = Low | √ | |
| Thermal shutdown | TJ > TJSD | √ | |
| UVLO | 0.7 V < VIN < VUVLO | √ | |
| Power supply removal | VIN < 0.7 V | √ | |
The PG signal can be used for sequencing of multiple rails by connecting the PG signal to the EN pin of other converters. Leave the PG pin unconnected when not used. The PG rising edge and falling edge has a 40 µs blanking time, as shown in Figure 7-7. At start-up, the delay of PG signal is typically 125 µs after soft start is finished.
Figure 7-7 Power-Good Behavior