ZHCSL99G September   2019  – January 2025 TPS62860 , TPS62861

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Soft Start
      2. 7.3.2 Output Voltage Selection (VSEL) for TPS62860x
      3. 7.3.3 Output Voltage Selection (VSEL and I2C)
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Power Good (PG)
      6. 7.3.6 Switch Current Limit and Short Circuit Protection
      7. 7.3.7 Thermal Shutdown
      8. 7.3.8 Output Voltage Discharge
    4. 7.4 Device Functional Modes
      1. 7.4.1 Smart Enable and Shutdown (EN)
      2. 7.4.2 Forced PWM Operation
      3. 7.4.3 Forced PWM Mode During Output Voltage Change
      4. 7.4.4 Power Save Mode
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard- and Fast-Mode Protocol
      3. 7.5.3 I2C Update Sequence
      4. 7.5.4 I2C Register Reset
  9. Register Map
    1. 8.1 I2C Address Byte
    2. 8.2 Register Address Byte
    3. 8.3 VOUT Register 1
    4. 8.4 VOUT Register 2
    5. 8.5 CONTROL Register
    6. 8.6 STATUS Register
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application, TPS628610
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
      3. 9.2.3 Application Curves
    3. 9.3 Typical Application, TPS628600, TPS62860x
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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Serial Interface Description

I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus Specification, Version .6, 2014). The bus consists of a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA and SCL. A controller device, usually a microcontroller or a digital signal processor, controls the bus. The controller is responsible for generating the SCL signal and device addresses. The controller also generates specific conditions that indicate the START and STOP of data transfer. A target device receives, transmits data, or both on the bus under control of the controller device.

The TPS6286x device works as a target and supports the following data transfer modes, as defined in the I2C-Bus Specification: standard mode (100 kbps), fast mode (400 kbps), and fast mode plus (1 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new values depending on the instantaneous application requirements. Register contents remain intact as long as the input voltage remains above 1.8 V.

The data transfer protocol for standard and fast modes is exactly the same, therefore, the modes are referred to as F/S-mode in this document. The protocol for high-speed mode is different and must not be used.

TI recommends that the I2C controller initiates a STOP condition on the I2C bus after the initial power up of SDA and SCL pullup voltages to make sure of reset of the I2C engine.