A proper layout is critical for the
operation of any switched mode power supply, especially at high switching
frequencies. The PCB layout of the TPS62865 and TPS62867 devices requires careful
attention to ensure best performance. A poor layout can lead to issues like bad line
and load regulation, instability, increased EMI radiation, and noise sensitivity.
Refer to the Five Steps to a Great PCB Layout for a Step-Down
Converter technical brief for a detailed discussion of general
best practices. The following are specific recommendations for the TPS62865 and
TPS62867:
- The input capacitor or
capacitors must be placed as close as possible to the VIN and PGND pins of
the device. This is the most critical component placement. Route the input
capacitor or capacitors directly to the VIN and PGND pins, avoiding
vias.
- Place the output inductor close to the SW pins. Minimize the copper area at
the switch node.
- Place the output capacitor or
capacitors ground close to the PGND pin and route it directly, avoiding
vias. Minimize the length of the connection from the inductor to the output
capacitor. Connect the VOS pin directly to the output capacitor.
- Sensitive traces, such as the connections to the VOS, FB, and VSEL pins,
must be connected with short traces and be routed away from any noise
source, such as the SW pin.
- Make the connections from the
input voltage of the system and the connection to the load as wide as
possible to minimize voltage drops.
- Have a solid ground plane between PGND and the input and output capacitor
ground connections.
- The sensitive signal ground
connections for the feedback voltage divider must be connected to a separate
signal ground trace.