During device initialization, a resistor-to-digital converter in the device determines the state of the FSEL pin and sets the switching frequency of the DC/DC converter according to Table 8-2.

1. For a reliable voltage setting, make sure there is no stray current path connected to the FSEL pin and that the parasitic capacitance between the FSEL pin and GND is less than 100pF.

Figure 8-10 shows a simplified block diagram of the R2D converter used to detect the state of the FSEL pin (an identical circuit detects the state of the VSEL pin – see Section 8.3.6.2).

Figure 8-10 FSEL R2D Converter Functional Block Diagram

Detection of the state of the FSEL pin works as follows:

To detect the most significant bit (MSB), the circuit opens S1 and S2, and the input buffer detects if a high or a low level is connected to the FSEL pin.

To detect the least significant bit (LSB):

• If the MSB was 0, the circuit closes S1. If the input buffer detects a high level, LSB = 1. If the circuit detects a low level, LSB = 0.
• If the MSB was 1, the circuit closes S2. If the input buffer detects a low level, LSB = 0. If the circuit detects a high level, LSB = 1.