A high level on the MODE/SYNC pin selects forced PWM operation. A low level on the MODE/SYNC pin selects power save operation, in which, the device automatically transitions between PWM and PFM, according to the load conditions.

If the user applies a valid clock signal to the MODE/SYNC pin, the device synchronizes the switching cycles to the external clock and automatically selects forced PWM operation.

The MODE/SYNC pin is logically ORed with the FPWMEN bit in the CONTROL1 register (see Table 8-1).

When multiple devices are used together in a stacked configuration, the MODE/SYNC pin of the secondary devices is the input for the clock signal (see Section 8.3.17).