ZHCSQI6C May 2022 – October 2023 TPS62870-Q1 , TPS62871-Q1 , TPS62872-Q1 , TPS62873-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 说明（续）
- 6 Device Options
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Fixed-Frequency DCS Control Topology
- 9.3.2 Forced PWM and Power Save Modes
- 9.3.3 Precise Enable
- 9.3.4 Start-Up
- 9.3.5 Switching Frequency Selection
- 9.3.6 Output Voltage Setting
- 9.3.7 Compensation (COMP)
- 9.3.8 Mode Selection and Clock Synchronization (MODE/SYNC)
- 9.3.9 Spread Spectrum Clocking (SSC)
- 9.3.10 Output Discharge
- 9.3.11 Undervoltage Lockout (UVLO)
- 9.3.12 Overvoltage Lockout (OVLO)
- 9.3.13 Overcurrent Protection
- 9.3.14 Power Good (PG)
- 9.3.15 Remote Sense
- 9.3.16 Thermal Warning and Shutdown
- 9.3.17 Stacked Operation
- 9.4 Device Functional Modes
- 9.5 Programming
- 9.6 Register Map
- 10Application and Implementation
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
9.3.1 Fixed-Frequency DCS Control Topology
Figure 9-1 shows a simplified block diagram of the fixed-frequency enhanced DCS control topology used in the TPS6287x-Q1 devices. This topology is comprised of an inner emulated current loop, a middle direct feedback loop, and an outer voltage-regulating loop.
Figure 9-1 Fixed-Frequency DCS Control Topology (Simplified)