ZHCSQI6C May 2022 – October 2023 TPS62870-Q1 , TPS62871-Q1 , TPS62872-Q1 , TPS62873-Q1
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 说明（续）
- 6 Device Options
- 7 Pin Configuration and Functions
- 8 Specifications
-
9 Detailed Description
- 9.1 Overview
- 9.2 Functional Block Diagram
- 9.3
Feature Description
- 9.3.1 Fixed-Frequency DCS Control Topology
- 9.3.2 Forced PWM and Power Save Modes
- 9.3.3 Precise Enable
- 9.3.4 Start-Up
- 9.3.5 Switching Frequency Selection
- 9.3.6 Output Voltage Setting
- 9.3.7 Compensation (COMP)
- 9.3.8 Mode Selection and Clock Synchronization (MODE/SYNC)
- 9.3.9 Spread Spectrum Clocking (SSC)
- 9.3.10 Output Discharge
- 9.3.11 Undervoltage Lockout (UVLO)
- 9.3.12 Overvoltage Lockout (OVLO)
- 9.3.13 Overcurrent Protection
- 9.3.14 Power Good (PG)
- 9.3.15 Remote Sense
- 9.3.16 Thermal Warning and Shutdown
- 9.3.17 Stacked Operation
- 9.4 Device Functional Modes
- 9.5 Programming
- 9.6 Register Map
- 10Application and Implementation
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
9.3.14.1 Standalone or Primary Device Behavior
The primary purpose of the PG pin is to indicate if the output voltage is in regulation, but it also indicates if the device is in thermal shutdown or disabled. Table 9-7 summarizes the behavior of the PG pin in a standalone or primary device.
| VIN | EN | VOUT | Soft Start | PGBLNKDVS | TJ | PG |
|---|---|---|---|---|---|---|
| 2 V > VIN | X | X | X | X | X | Undefined |
| VIT(UVLO) ≥ VIN ≥ 2 V | X | X | X | X | X | Low |
| VIN > VIT(UVLO) | L | X | X | X | X | Low |
| H | X | Active | X | X | Low | |
| VOUT > VT(PGOV) or < VT(PGUV) > VOUT |
Inactive | 0 | X | low | ||
| 1 (and DVS is active) |
TJ < TSD | Hi-Z | ||||
| VT(PGOV) > VOUT > VT(PGUV) | X | TJ < TSD | Hi-Z | |||
| X | X | X | TJ > TSD | Low |
Figure 9-12 shows a functional block diagram of the power-good function in a standalone or primary device. A window comparator monitors the output voltage, and the output of the comparator goes high if the output voltage is either less than 95% (typical) or greater than 105% (typical) of the nominal output voltage. The output of the window comparator is deglitched – the typical deglitch time is 40 µs – and then used to drive the open-drain PG pin.
Figure 9-12 Power-Good Functional Block Diagram (Standalone or Primary Device)
During DVS activity, when the DC/DC converter transitions from one output voltage setting to another, the output voltage can temporarily exceed the limits of the window comparator and pull the PG pin low. The device has a feature to disable this behavior. If PGBLNKDVS = 1 in the CONTROL3 register, the device ignores the output of the power-good window comparator while DVS is active.
Note that the PG pin is always low, regardless of the output of the window comparator, when:
- The device is in thermal shutdown.
- The device is disabled.
- The device is in undervoltage lockout.
- The device is in soft start.