ZHCSQJ5A may   2022  – march 2023 TPS62903-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Mode Selection and Device Configuration MODE/S-CONF
      2. 8.3.2  Adjustable VO Operation (External Voltage Divider)
      3. 8.3.3  Selectable VO Operation (VSET and Internal Voltage Divider)
      4. 8.3.4  Soft Start and Tracking (SS/TR)
        1. 8.3.4.1 Tracking Function
      5. 8.3.5  Smart Enable with Precise Threshold
      6. 8.3.6  Power Good (PG)
      7. 8.3.7  Output Discharge Function
      8. 8.3.8  Undervoltage Lockout (UVLO)
      9. 8.3.9  Current Limit and Short-Circuit Protection
      10. 8.3.10 High Temperature Specifications
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Forced Pulse Width Modulation (FPWM) Operation
      2. 8.4.2 Power Save Mode Operation (Auto PFM and PWM)
      3. 8.4.3 AEE (Automatic Efficiency Enhancement)
      4. 8.4.4 100% Duty-Cycle Operation
      5. 8.4.5 Starting into a Prebiased Load
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application with Adjustable Output Voltage
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Programming the Output Voltage
        3. 9.2.2.3 External Component Selection
          1. 9.2.2.3.1 Output Filter and Loop Stability
          2. 9.2.2.3.2 Inductor Selection
          3. 9.2.2.3.3 Capacitor Selection
            1. 9.2.2.3.3.1 Output Capacitor
            2. 9.2.2.3.3.2 Input Capacitor
            3. 9.2.2.3.3.3 Soft-Start Capacitor
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Application Curves Vout = 1.8 V
        2. 9.2.3.2 Application Curves Vout = 1.2 V
        3. 9.2.3.3 Application Curves Vout = 0.6 V
    3. 9.3 Typical Application with Selectable VOUT using VSET
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
        1. 9.3.2.1 Programming the Output Voltage
      3. 9.3.3 Application Curves
        1. 9.3.3.1 Application Curves Vout = 5 V
        2. 9.3.3.2 Application Curves Vout = 3.3 V
    4. 9.4 System Examples
      1. 9.4.1 LED Power Supply
      2. 9.4.2 Powering Multiple Loads
      3. 9.4.3 Voltage Tracking
      4. 9.4.4 Inverting Buck-Boost (IBB)
    5. 9.5 Power Supply Recommendations
    6. 9.6 Layout
      1. 9.6.1 Layout Guidelines
      2. 9.6.2 Layout Example
      3. 9.6.3 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design With WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.4.4 100% Duty-Cycle Operation

The duty cycle of the buck converter operating in PWM mode is given as D = VOUT / VIN. The duty cycle increases as the input voltage comes close to the output voltage and the off time gets smaller. When the minimum off time of typically 80 ns is reached, the TPS62903-Q1 scales down its switching frequency while it approaches 100% mode. In 100% mode, the device keeps the high-side switch on continuously. The high-side switch stays turned on as long as the output voltage is below the internal set point, allowing the conversion of small input to output voltage differences (for example, getting longest operation time of battery-powered applications). In 100% duty cycle mode, the low-side FET is switched off.

The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, can be calculated as:

Equation 10. V I N   ( M I N ) = V O U T + I O U T × R D S ( O N )   +   R L

where

  • IOUT is the output current.
  • RDS(on) is the on-state resistance of the high-side FET.
  • RL is the DC resistance of the inductor used.
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP | 米乐app下载官网（中国）|ios|Android/通用版APP最新版 | 米乐|米乐·M6（中国大陆）官方网站 | 千亿体育登陆地址 | 华体会体育（中国）HTH·官方网站 | 千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载 | 18新利网v1.2.5|中国官方网站 | bob电竞真人（中国官网）安卓/ios苹果/电脑版【1.97.95版下载】 | 千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装 |