ZHCSO67 March 2022 TPS629206
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Mode Selection and Device Configuration (MODE/S-CONF Pin)
- 8.3.2 Adjustable VO Operation (External Voltage Divider)
- 8.3.3 Selectable VO Operation (VSET and Internal Voltage Divider)
- 8.3.4 Smart Enable with Precise Threshold
- 8.3.5 Power Good (PG)
- 8.3.6 Output Discharge Function
- 8.3.7 Undervoltage Lockout (UVLO)
- 8.3.8 Current Limit and Short Circuit Protection
- 8.3.9 Thermal Shutdown
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
8.4.4 100% Duty-Cycle Operation
The duty cycle of the buck converter operated in PWM mode is given in Equation 10.
The duty cycle increases as the input voltage comes close to the output voltage and the off time of the high-side switch gets smaller. When the minimum off time of typically 80 ns is reached, the TPS629206 scales down its switching frequency while it approaches 100% mode. In 100% mode, the device keeps the high-side switch on continuously as long as the output voltage is below the internal set point. This allows the conversion of small input to output voltage differences. For example, getting the longest operation time of battery-powered applications. In 100% duty cycle mode, the low-side FET is switched off.
The minimum input voltage to maintain output voltage regulation, depending on the load current and the output voltage level, can be calculated as:
where:
- IOUT is the output current.
- RDS(on) is the on-state resistance of the high-side FET.
- RL is the DC resistance of the inductor used.