ZHCSQD3A october 2022 – march 2023 TPS62992-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
SUPPLY | ||||||
IQ | Operating Quiescent Current (Power Save Mode) | Iout = 0 mA device not switching | 4 | µA | ||
IQ;PWM | Operating Quiescent Current (PWM Mode) | VIN= 6V, VOUT=1.2V; Iout = 0 mA, device switching | 8 | mA | ||
ISD | Shutdown current into VIN pin | EN = 0 V, | 0.27 | 3.5 | µA | |
VUVLO | Under Voltage Lock-Out | VIN rising, | 2.85 | 2.925 | 3.0 | V |
Under Voltage Lock-Out | VIN falling | 2.71 | 2.79 | 2.87 | V | |
VUVLO | Under Voltage Lock-Out Hysteresis | 130 | mV | |||
CONTROL & INTERFACE | ||||||
ILKG | EN Input leakage current | EN = 5V | 10 | 310 | nA | |
VIH;MODE | High-Level Input Voltage at MODE/S-CONF Pin | 1.0 | V | |||
VIL;MODE | Low-Level Input Voltage at MODE/S-CONF Pin | 0.15 | V | |||
TSD | Thermal Shutdown Threshold | TJ rising | 168 | 175 | 185 | °C |
Thermal Shutdown Hysteresis | TJ falling | 12.5 | ||||
VIH | High-level input voltage at EN-Pin | 0.97 | 1.0 | 1.03 | V | |
VIL | Low-level input voltage at EN-Pin | 0.820 | 0.850 | 0.880 | V | |
VPG | Power good fthreshold | VFB rising, referenced to VFB nominal | 93% | 96% | 99% | |
VFB falling, referenced to VFB nominal | 88% | 92% | 96% | |||
VPG_HYS | Power good threshold hysteresis | 1.5% | 3.5% | 6% | ||
VPG,OL | Low-level output voltage at PG pin | ISINK = 1 mA | 0.4 | V | ||
IPG,LKG | Input leakage current into PG pin | VPG = 5 V, | 25 | 550 | nA | |
tPG,DLY | Power good delay time | VFB rising and falling | 32 | µs | ||
CSET | Maximum Capacitance connected to VSET pin | 30 | pF | |||
POWER SWITCHES | ||||||
ILKG;SW | Leakage current into SW-Pin | EN = 0V, VSW = VOS = 5.5V, TJ up to 150°C | 2 | 7 | µA | |
RDS;ON | High-side FET on resistance | VIN > 4 V, ISW = 500 mA | 62 | 111 | mΩ | |
Low-side FET on resistance | VIN > 4 V, ISW = 500 mA | 22 | 41 | |||
ILIM | High-side FET current limit | 2.7 | 3.1 | 3.7 | A | |
ILIM | Low-side FET current limit | 2.5 | 3 | 3.5 | A | |
ILIM;SINK | Low-side FET sink current limit | 1.3 | 1.7 | 2.5 | A | |
fSW | Switching frequency | 2.5-MHz selection | 2.5 | MHz | ||
TON(MIN) | Minimum On-time | 30 | ns | |||
fSW | Switching frequency | 1.0-MHz selection | 1.0 | MHz | ||
OUTPUT | ||||||
VO | Output Voltage Regulation | VSET Configuration selected, TJ = 25°C | –1% | +1% | ||
VO | Output Voltage Regulation | VSET Configuration selected | –1.5% | +1.5% | ||
VFB | Feedback Regulation Voltage | Adjustable Configuration selected | 0.6 | V | ||
VFB | Feedback Voltage Regulation | FB-Option selected. TJ = 25 °C. | –0.6% | +0.6% | ||
VFB | Feedback Voltage Regulation | FB-Option selected | –1.25% | +1.25% | ||
IFB | Input leakage current into FB pin | Adjustable configuration, VFB = 0.6 V | 1 | 70 | nA | |
Tdelay | Start-up delay time | IO = 0 mA, time from EN=HIGH until start switching, Adjustable Configuration selected | 600 | 1400 | µs | |
Start-up delay time | IO = 0 mA, time from EN=HIGH until start switching, VSET Configuration selected. The typical value is based on the first option of VSET configuration. | 650 | 1850 | µs | ||
TSS | Soft-Start time | IO = 0 mA after Tdelay, from 1st switching pulse until target VO , Css=Open | 150 | µs | ||
ISS | SS/TR source current | 2.25 | 2.5 | 2.75 | µA | |
VFB/VSS/TR | Tracking Gain, Adjustable Configuration | 0.75 | ||||
VFB/VSS/TR | Tracking Gain tolerance | ±8 | mV | |||
RDISCH | Active Discharge Resistance | Discharge = ON - Option Selected, EN = LOW | 7.5 | 30 | Ω |