12.1 Layout Guidelines

• The VINDCDC and VINLDOx pins must be bypassed to ground with a low-ESR ceramic bypass capacitor. TI recommends the typical bypass capacitance is 10 μF and 2.2 μF with a X5R dielectric.
• The optimum placement is closest to the VINDCDCx and VINLDOx pins of the device. Minimize the loop area formed by the bypass capacitor connection, the VINDCDC and VINLDO pins, and the thermal pad of the device.
• The thermal pad must be tied to the PCB ground plane with multiple vias.
• The VLDOx and VDCDCx pins (feedback pins) traces must be routed away from any potential noise source to avoid coupling.
• VODC output capacitance must be placed immediately at the VODC pin. Excessive distance between the capacitance and DCDCx pin may cause poor converter performance.
• AGND star back to PGND as close to IC as possible.
• DGND connect to thermal pad.

12.2 Layout Example

Figure 34. Layout Recommendation

Figure 35. Bypass Capacitor and Via Placement Recommendation