9.2.2.1 Inductor Selection for the DC-DC Converters

Each of the converters in the TPS65020 typically use a 3.3-μH output inductor. Larger or smaller inductor values are used to optimize the performance of the device for specific operation conditions. The selected inductor has to be rated for its DC resistance and saturation current. The DC resistance of the inductance influences directly the efficiency of the converter. Therefore, an inductor with lowest DC resistance must be selected for highest efficiency.

For a fast transient response, a 2.2-μH inductor in combination with a 22-μF output capacitor is recommended.

Equation 8 calculates the maximum inductor current under static load conditions. The saturation current of the inductor must be rated higher than the maximum inductor current as calculated with Equation 8. This is needed because during heavy-load transient the inductor current rises above the value calculated under Equation 8.

Equation 8.

Equation 9.

where

• f = Switching Frequency (1.5 MHz typical)
• L = Inductor Value
• ΔI_L = Peak-to-Peak inductor ripple current
• I_LMAX = Maximum Inductor current

The highest inductor current occurs at maximum Vin.

Open-core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents versus a comparable shielded inductor.

A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS65020 (2 A for the VDCDC1 and VDCDC2 converters, and 1.3 A for the VDCDC3 converter). The core material from inductor to inductor differs and has an impact on the efficiency especially at high switching frequencies.

See Table 16 and the typical applications for possible inductors.

9.2.2.2 Output Capacitor Selection

The advanced fast response voltage mode control scheme of the inductive converters implemented in the TPS65020 allow the use of small ceramic capacitors with a typical value of 10 μF for a 3.3-μH inductor for each converter without having large output voltage under and overshoots during heavy-load transients.

For a fast transient response a 22-μF capacitor with a 2.2-μH inductor must be used on each converter.

Ceramic capacitors having low ESR values have the lowest output voltage ripple and are recommended. See Table 17 for recommended components.

If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application requirements. Just for completeness, the RMS ripple current is calculated in Equation 10.

Equation 10.

At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and discharging the output capacitor:

Equation 11.

where

• the highest output voltage ripple occurs at the highest input voltage V_in

At light-load currents, the converters operate in PSM and the output voltage ripple is dependent on the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The typical output voltage ripple is less than 1% of the nominal output voltage.

9.2.2.3 Input Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. Each DC-DC converter requires a 10-μF ceramic input capacitor on its input pin VINDCDCx. The input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the input for the DC-DC converters. A filter resistor of up to 10R and a 1-μF capacitor is used for decoupling the VCC pin from switching noise. Note that the filter resistor may affect the UVLO threshold because up to 3 mA can flow through this resistor into the VCC pin when all converters are running in PWM mode.

9.2.2.4 Output Voltage Selection

The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down converter. See the table for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 38.

The output voltage of VDCDC3 is set with the I²C interface. If the voltage is changed from the default, using the DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC3 does not change the voltage set with the register. Bit B6 in the CON_CTRL2 register is used to switch between the internal voltage setting or the voltage set with the external DEFDCDC3 pin for the VDCDC3 converter.

Figure 38 illustrations how to use an external resistor divider at DEFDCDCx.

Figure 38. External Resistor Divider

When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input voltage V_(bat). The total resistance (R1+R2) of the voltage divider must be kept in the 1-MR range to maintain a high efficiency at light load.

V_(DEFDCDCx) = 0.6 V

Equation 12.

9.2.2.5 VRTC Output

The VRTC output is typically connected to the V_CC_Batt pin of a Intel PXA270 processor. During power-up of the processor, the TPS65020 internally switches from the LDO or the backup battery to the system voltage connected at the VSYSIN pin (see Figure 30). It is required to add a capacitor of 4.7-μF minimum to the VRTC pin, even the output may be unused.

9.2.2.6 LDO1 and LDO2

The LDOs default voltage is 1.1 V for LDO2 and 1.3 V for LDO1. They are intended to provide power to VCC_PLL and the VCC_SRAM pin on a PXA270 processor. The minimum output capacitor required is 2.2 μF. The LDOs output voltage is changed to different voltages between 1 V and 3.3 V using the I²C interface. Therefore, they can also be used as general-purpose LDOs in applications powering processors different from PXA270. The supply voltage for the LDOs needs to be connected to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system, and providing the highest efficiency.

9.2.2.7 TRESPWRON

This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V. The timing is generated by charging and discharging the capacitor with a current of 2 μA between a threshold of 0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms.

While there is no real upper and lower limit for the capacitor connected to TRESPWRON, TI recommends not leaving signal pins open.

Equation 13.

where

• t_(reset) is the reset delay time
• C_(reset) is the capacitor connected to the TRESPWRON pin

The minimum and maximum values for the timing parameters called ICONST (2 µA), TRESPWRON_UPTH
(1 V), and TRESPWRON_LOWTH (0.25 V) can be found under the Electrical Characteristics.

9.2.2.8 VCC Filter

An RC filter connected at the VCC input is used to prevent noise from the internal supply for the bandgap and other analog circuitry. A typical resistor value of 1 Ω and 1 μF is used to filter the switching spikes generated by the DC-DC converters. A resistor larger than 10 Ω must not be used because the current (up to 3 mA) into VCC causes a voltage drop at the resistor. This causes the undervoltage lockout circuitry connected internally at VCC to switch off too early.

Table 19. Inductor and Output Capacitor Combinations