ZHCSIH9F March   2009  – July 2018 TPS65023-Q1

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
      2. 8.3.2 Soft Start
      3. 8.3.3 Active Discharge When Disabled
      4. 8.3.4 Power-Good Monitoring
      5. 8.3.5 Low-Dropout Voltage Regulators
      6. 8.3.6 Undervoltage Lockout
    4. 8.4 Device Functional Modes
      1. 8.4.1 VRTC Output and Operation With or Without Backup Battery
      2. 8.4.2 Power-Save Mode Operation (PSM)
      3. 8.4.3 Low-Ripple Mode
      4. 8.4.4 100% Duty-Cycle Low-Dropout Operation
      5. 8.4.5 System Reset and Control Signals
        1. 8.4.5.1 DEFLDO1 and DEFLDO2
        2. 8.4.5.2 Interrupt Management and the INT Pin
    5. 8.5 Programming
      1. 8.5.1 Power-Up Sequencing
      2. 8.5.2 Serial Interface
    6. 8.6 Register Maps
      1. 8.6.1 VERSION Register (address: 00h) Read-Only
      2. 8.6.2 PGOODZ Register (address: 01h) Read-Only
        1. Table 5. PGOODZ Register Field Descriptions
      3. 8.6.3 MASK Register (address: 02h)
      4. 8.6.4 REG_CTRL Register (address: 03h)
        1. Table 6. REG_CTRL Register Field Descriptions
      5. 8.6.5 CON_CTRL Register (address: 04h)
        1. Table 7. CON_CTRL Register Field Descriptions
      6. 8.6.6 CON_CTRL2 Register (address: 05h)
        1. Table 8. CON_CTRL2 Register Field Descriptions
      7. 8.6.7 DEFCORE Register (address: 06h)
        1. Table 9. DEFCORE Register Field Descriptions
      8. 8.6.8 DEFSLEW Register (address: 07h)
        1. Table 10. DEFSLEW Register Field Descriptions
      9. 8.6.9 LDO_CTRL Register (address: 08h)
        1. Table 11. LDO_CTRL Register Field Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Reset Condition of DCDC1
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection for the DC-DC Converters
        2. 9.2.2.2 Output Capacitor Selection
        3. 9.2.2.3 Input Capacitor Selection
        4. 9.2.2.4 Output Voltage Selection
        5. 9.2.2.5 VRTC Output
        6. 9.2.2.6 LDO1 and LDO2
        7. 9.2.2.7 TRESPWRON
        8. 9.2.2.8 VCC Filter
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 接收文档更新通知
    4. 12.4 社区资源
    5. 12.5 商标
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.5 Electrical Characteristics

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 125°C, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CONTROL SIGNALS: SCLK, SDAT (INPUT), DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2
VIH High-level input voltage Resistor pullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 1.3 VCC V
VIH High-level input voltage, SDAT Resistor pullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 1.45 VCC V
VIL Low-level input voltage Resistor pullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 0 0.4 V
IH Input bias current 0.01 0.1 μA
CONTROL SIGNALS: HOT_RESET
VIH High-level input voltage 1.3 VCC V
VIL Low-level input voltage 0 0.4 V
IIB Input bias current 0.01 0.1 μA
tglitch Deglitch time at HOT_RESET 25 30 35 ms
CONTROL SIGNALS: LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (OUTPUT)
VOH High-level output voltage 6 V
VOL Low-level output voltage IIL = 5 mA 0 0.3 V
Duration of low pulse at RESPWRON External capacitor 1 nF 100 ms
Reset power-on threshold VRTC falling –3% 2.4 3% V
VRTC rising –3% 2.52 3%
SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3
I(q) Operating quiescent current, PFM All three DC-DC converters enabled, zero load, no switching, and LDOs enabled VCC = 3.6 V,
VBACKUP = 3 V,
VSYSIN = 0 V		 85 100 μA
All three DC-DC converters enabled, zero load, no switching, and LDOs off VCC = 3.6 V,
VBACKUP = 3 V,
VSYSIN = 0 V		 78 90
DCDC1 and DCDC2 converters enabled, zero load, no switching, and LDOs off VCC = 3.6 V,
VBACKUP = 3 V,
VSYSIN = 0 V		 57 70
DCDC1 converter enabled, zero load, no switching, and LDOs off VCC = 3.6 V,
VBACKUP = 3 V,
VSYSIN = 0 V		 43 55
II Current into VCC, PWM All three DC-DC converters enabled and running in PWM, LDOs off VCC = 3.6 V,
VBACKUP = 3 V,
VSYSIN = 0 V		 2 3 mA
DCDC1 and DCDC2 converters enabled and running in PWM, LDOs off VCC = 3.6 V,
VBACKUP = 3 V,
VSYSIN = 0 V		 1.5 2.5
DCDC1 converter enabled and running in PWM, LDOs off VCC = 3.6 V,
VBACKUP = 3 V,
VSYSIN = 0 V		 0.85 2
I(q) Quiescent current All converters disabled, LDOs off VCC = 3.6 V,
VBACKUP = 3 V,
VSYSIN = 0 V		 23 33 μA
VCC = 2.6 V,
VBACKUP = 3 V,
VSYSIN = 0 V		 3.5 5
VCC = 3.6 V,
VBACKUP = 0 V,
VSYSIN = 0 V		 43
SUPPLY PINS: VBACKUP, VSYSIN, VRTC
I(q) Operating quiescent current VBACKUP = 3 V, VSYSIN = 0 V, VCC = 2.6 V,
current into VBACKUP		 20 33 μA
I(SD) Operating quiescent current VBACKUP < V_VBACKUP, current into VBACKUP 2 3 μA
VRTC LDO output voltage VSYSIN = VBACKUP = 0 V, IO = 0 mA 3 V
IO Output current for VRTC VSYSIN < 2.57 V and VBACKUP < 2.57 V 30 mA
VRTC short-circuit current limit VRTC = GND, VSYSIN = VBACKUP = 0 V 100 mA
Maximum output current at VRTC for
RESPWRON = 1		 VRTC > 2.6 V, VCC = 3 V, VSYSIN = VBACKUP = 0 V 30 mA
VO Output voltage accuracy for VRTC VSYSIN = VBACKUP = 0 V, IO = 0 mA –1% 1%
Line regulation for VRTC VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA –1% 1%
Load regulation VRTC IO = 1 mA to 30 mA, VSYSIN = VBACKUP = 0 V –3% 1%
Regulation time for VRTC Load change from 10% to 90% 10 μs
Ilkg Input leakage current at VSYSIN VSYSIN < V_VSYSIN 2 μA
rDS(on) of VSYSIN switch 12.5 Ω
rDS(on) of VBACKUP switch 12.5 Ω
Input voltage range at VBACKUP(1) 2.73 3.75 V
Input voltage range at VSYSIN(1) 2.73 3.75 V
VSYSIN threshold VSYSIN falling –3% 2.55 3% V
VSYSIN threshold VSYSIN rising –3% 2.65 3% V
VBACKUP threshold VBACKUP falling –3% 2.55 3% V
VBACKUP threshold VBACKUP falling –3% 2.65 3% V
SUPPLY PIN: VINLDO
I(q) Operating quiescent current Current per LDO into VINLDO 16 30 μA
I(SD) Shutdown current Total current for both LDOs into VINLDO, VINLDO = 0 V 0.1 1 μA
VDCDC1 STEP-DOWN CONVERTER
IO Maximum output current 1500 mA
I(SD) Shutdown supply current in VINDCDC1 DCDC1_EN = GND 0.1 1 μA
rDS(on) P-channel MOSFET on-resistance VCC = V(GS) = 3.6 V 125 261 mΩ
Ilkg P-channel leakage current VCC = 6 V 2 μA
rDS(on) N-channel MOSFET on-resistance VCC = V(GS) = 3.6 V 130 260 mΩ
Ilkg N-channel leakage current V(DS) = 6 V 7 10 μA
Forward current limit (P-channel and N-channel) 2.5 V < VI(MAIN) < 6 V 1.9 2.19 2.6 A
fS Oscillator frequency 1.95 2.25 2.55 MHz
Fixed output voltage FPWMDCDC1 = 0 All VDCDC1 VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1.5 A –2% 2%
Fixed output voltage FPWMDCDC1 = 1 VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1.5 A –1% 1%
Adjustable output voltage with resistor divider at DEFDCDC1, FPWMDCDC1 = 0 VCC = VDCDC1 + 0.3 V (minimum 2.5 V) to 6 V,
0 mA ≤ IO ≤ 1.2 A		 –2% 2%
Adjustable output voltage with resistor divider at DEFDCDC1, FPWMDCDC1 = 1 VCC = VDCDC1 + 0.3 V (minimum 2.5 V) to 6 V,
0 mA ≤ IO ≤ 1.2 A		 –1% 1%
Line regulation VCC = VDCDC1 + 0.3 V (minimum. 2.5 V) to 6 V, IO = 10 mA 0 %/V
Load regulation IO = 10 mA to 1200 mA 0.25 %/A
Soft-start ramp time VDCDC1 ramping from 5% to 95% of target value 750 μs
Internal resistance from L1 to GND 1 MΩ
VDCDC1 discharge resistance DCDC1 discharge = 1 300 Ω
VDCDC2 STEP-DOWN CONVERTER
IO Maximum output current DEFDCDC2 = GND 1200 mA
VCC = 3.6 V, 3.3 V – 1% ≤ VDCDC2 ≤ 3.3 V + 1% 1000
I(SD) Shutdown supply current in VINDCDC2 DCDC2_EN = GND 0.1 1 μA
rDS(on) P-channel MOSFET on-resistance VCC = V(GS) = 3.6 V 140 300 mΩ
Ilkg P-channel leakage current VCC = 6 V 2 μA
rDS(on) N-channel MOSFET on-resistance VCC = V(GS) = 3.6 V 150 297 mΩ
Ilkg N-channel leakage current V(DS) = 6 V 7 10 μA
ILIMF Forward current limit (P-channel and N-channel) 2.5 V < VCC < 6 V 1.7 1.94 2.2 A
fS Oscillator frequency 1.95 2.25 2.55 MHz
Fixed output voltage FPWMDCDC2=0 VDCDC2 = 1.8 V VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1.2 A –2% 2%
VDCDC2 = 3.3 V VCC = 3.7 V to 6 V, 0 mA ≤ IO ≤ 1.2 A –1% 1%
Fixed output voltage FPWMDCDC2=1 VDCDC2 = 1.8 V VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1.2 A –2% 2%
VDCDC2 = 3.3 V VCC = 3.7 V to 6 V, 0 mA ≤ IO ≤ 1.2 A –1% 1%
Adjustable output voltage with resistor divider at DEFDCDC2 FPWMDCDC2 = 0 VCC = VDCDC2 + 0.3 V (minimum 2.5 V) to 6 V,
0 mA ≤ IO ≤ 1 A		 –2% 2%
Adjustable output voltage with resistor divider at DEFDCDC2, FPWMDCDC2 = 1 VCC = VDCDC2 + 0.3 V (minimum 2.5 V) to 6 V,
0 mA ≤ IO ≤ 1 A		 –1% 1%
Line regulation VCC = VDCDC2 + 0.3 V (minimum. 2.5 V) to 6 V, IO = 10 mA 0 %/V
Load regulation IO = 10 mA to 1000 mA 0.25 %/A
Soft-start ramp time VDCDC2 ramping from 5% to 95% of target value 750 μs
Internal resistance from L2 to GND 1 MΩ
VDCDC2 discharge resistance DCDC2 discharge = 1 300 Ω
VDCDC3 STEP-DOWN CONVERTER
IO Maximum output current DEFDCDC3 = GND 1000 mA
VCC = 3.6 V, 3.3 V – 1% ≤ VDCDC3 ≤ 3.3 V + 1% 525
I(SD) Shutdown supply current in VINDCDC3 DCDC3_EN = GND 0.1 1 μA
rDS(on) P-channel MOSFET on-resistance VCC = V(GS) = 3.6 V 310 698 mΩ
Ilkg P-channel leakage current VCC = 6 V 0.1 2 μA
rDS(on) N-channel MOSFET on-resistance VCC = V(GS) = 3.6 V 220 503 mΩ
Ilkg N-channel leakage current V(DS) = 6 V 7 10 μA
Forward current limit (P-channel and N-channel) 2.5 V < VCC < 6 V 1.28 1.49 1.69 A
fS Oscillator frequency 1.95 2.25 2.55 MHz
Fixed output voltage FPWMDCDC3=0 VDCDC3 = 1.8 V VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1 A –2% 2%
VDCDC3 = 3.3 V VCC = 3.6 V to 6 V, 0 mA ≤ IO ≤ 1 A –1% 1%
Fixed output voltage FPWMDCDC3=1 VDCDC3 = 1.8 V VCC = 2.5 V to 6 V, 0 mA ≤ IO ≤ 1 A –2% 2%
VDCDC3 = 3.3 V VCC = 3.6 V to 6 V, 0 mA ≤ IO ≤ 1 A –1% 1%
Adjustable output voltage with resistor divider at DEFDCDC3 FPWMDCDC3 = 0 VCC = VDCDC3 + 0.5 V (minimum 2.5 V) to 6 V,
0 mA ≤ IO ≤ 800 mA		 –2% 2%
Adjustable output voltage with resistor divider at DEFDCDC3, FPWMDCDC3 = 1 VCC = VDCDC3 + 0.5 V (minimum 2.5 V) to 6 V,
0 mA ≤ IO ≤ 800 mA		 –1% 1%
Line regulation VCC = VDCDC3 + 0.3 V (minimum. 2.5 V) to 6 V, IO = 10 mA 0 %/V
Load regulation IO = 10 mA to 1000 mA 0.25 %/A
Soft-start ramp time VDCDC3 ramping from 5% to 95% of target value 750 μs
Internal resistance from L3 to GND 1 MΩ
VDCDC3 discharge resistance DCDC3 discharge = 1 300 Ω
VLDO1 AND VLDO2 LOW DROPOUT REGULATORS
VI Input voltage range for LDO1, 2 1.5 6.5 V
VO(LD01) LDO1 output voltage range 1 3.15 V
VO(LDO2) LDO2 output voltage range 1 3.3 V
IO Maximum output current for LDO1, LDO2 VCC = 1.8 V, VO = 1.3 V 200 mA
VCC = 1.5 V, VO = 1.3 V 120
I(SC) LDO1 and LDO2 short circuit current limit V(LDO1) = GND, V(LDO2) = GND 400 mA
Minimum voltage drop at LDO1, LDO2 IO = 50 mA, VINLDO = 1.8 V 120 mV
IO = 50 mA, VINLDO = 1.5 V 65 150
IO = 200 mA, VINLDO = 1.8 V 300
Output voltage accuracy for LDO1, LDO2 IO = 10 mA –2% 1%
Line regulation for LDO1, LDO2 VINLDO = VLDO1,2 + 0.5 V (minimum 2.5 V) to 6.5 V,
IO = 10 mA		 –1% 1%
Load regulation for LDO1, LDO2 IO = 0 mA to 50 mA –1% 1%
Regulation time for LDO1, LDO2 Load change from 10% to 90% 10 μs
ANALOG SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3
VIH High-level input voltage(2) 1.3 VCC V
VIL Low-level input voltage 0 0.1 V
Input bias current 0.001 0.05 μA
THERMAL SHUTDOWN
T(SD) Thermal shutdown Increasing junction temperature 160 °C
Thermal shutdown hysteresis Decreasing junction temperature 20 °C
INTERNAL UNDERVOLTAGE LOCK OUT
UVLO Internal UVLO VCC falling –2% 2.35 2% V
VUVLO_HYST Internal UVLO comparator hysteresis 120 mV
VOLTAGE DETECTOR COMPARATORS
Comparator threshold
(PWRFAIL_SNS, LOWBAT_SNS)		 Falling threshold –2% 1 2% V
Hysteresis 40 50 60 mV
Propagation delay 25-mV overdrive 10 μs
POWER GOOD
VPGOODF VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, decreasing –12% –10% –8%
VPGOODR VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, increasing –7% –5% –3%
(1) Based on the requirements for the Intel PXA270 processor.
(2) The input voltage can go as high as 6 V. If the input voltage exceeds VCC, an input current of (V(PB_IN) - 0.7 V - VCC) / 10 kΩ flows.
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