8.5.2 Serial Interface

The serial interface is compatible with the standard- and fast-mode I²C specifications, allowing transfers at up to 400 kHz. The interface adds flexibility to the power-supply solution, enabling most functions to be programmed to new values, depending on the instantaneous application requirements and charger status to be monitored. Register contents remain intact as long as V_CC remains above 2 V. The TPS65023-Q1 has a 7-bit address: 1001000; other addresses are available on contact with the factory. Attempting to read data from the register addresses not listed in this section results in FFh being read out.

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65023-Q1 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit. The TPS65023-Q1 device must pull down the DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this case, the slave TPS65023-Q1 device must leave the data line high to enable the master to generate the stop condition.

Figure 28. Bit Transfer on the Serial Interface

Figure 29. Start and Stop Conditions

Figure 30. Serial Interface Write to TPS65023-Q1 Device

Figure 31. Serial Interface Read from TPS65023-Q1: Protocol A

Figure 32. Serial Interface Read from TPS65023-Q1: Protocol B