The VINDCDC1, VINDCDC2 and VINDCDC3 terminals should be bypassed to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 10 uF ceramic with a X5R or X7R dielectric.
The VINLDO terminal should be bypassed to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 1 uF ceramic with a X5R or X7R dielectric.
The optimum placement is closest to the individual voltage terminals and the AGNDx terminals.
The AGNDx terminals should be tied to the pcb ground plane at the terminal of the IC.
The cross sectional area loop from the input capacitor to the VINDCDCx input and corresponding PGNDx terminal should be minimized as much as possible.
Route the feedback signal for each of the step-down converters next to the current path of the converter in order to decrease the cross sectional area of the feedback loop which minimizes noise injection into the loop.
Do not route any noise sensitive signals under or next to any of the step-down inductors. Ensure a keepout region directly under the inductors or at least provide ground shielding.
It is recommended to have the layer directly underneath the IC to be a solid copper ground plane.