8.1.1 DCDC1 Converter

The converter 1 output voltage is set by the status of the DEFLDO1 and DEFLDO2 pins. The pins can be pulled low, pulled high or left floating to allow 9 different logic states. See the description for the LDOs for further details. With the TPS65055 it is also possible to change the output voltage of converter DCDC1 through the I²C compatible interface. The VDCDC1 pin must be directly connected to V_OUT1 and no external resistor network may be connected.

8.1.2 DCDC2 Converter

The VDCDC2 pin must be directly connected to the DCDC2 converter output voltage. The DCDC2 converter output voltage can be selected through the DEFDCDC2 pin or the I²C compatible interface.

The DEFDCDC2 pin can either be connected to GND, or to V_CC. The converter 2 defaults to 1 V or 1.2 V depending on the logic level of the DEFDCDC2 pin. If DEFDCDC2 is tied to ground, the default is 1.2 V; if it is tied to V_CC, the default is 1 V.

With the TPS65055, the voltage can also be changed using the I²C registers – see Application and Implementation for details.

8.3.1 Power Save Mode

Power save mode is enabled per default and can be disabled using the I²C compatible interface. If the load current decreases, the converters enter power save mode operation automatically. During power save mode the converters operate with reduced switching frequency in PFM mode and with a minimum quiescent current to maintain high efficiency. The converter positions the output voltage typically 1% above the nominal output voltage. This voltage positioning feature minimizes voltage drops caused by a sudden load step.

To optimize converter efficiency at light load the average current is monitored, and if in PWM mode the inductor current remains below a certain threshold, then power save mode is entered. The typical threshold can be calculated according to:

Equation 1: Average output current threshold to enter PFM mode

Equation 2: Average output current threshold to leave PFM mode

During power save mode, the output voltage is monitored with a comparator. As the output voltage falls below the skip comparator threshold (skip comp) of V_OUTnominal +1%, the P-channel switch turns on and the converter effectively delivers a constant current as defined above. If the load is below the delivered current, then the output voltage rises until the same threshold is crossed again, whereupon all switching activity ceases, hence reducing the quiescent current to a minimum until the output voltage has dropped below the threshold again. If the load current is greater than the delivered current, then the output voltage falls until it crosses the skip comparator low (skip comp low) threshold set to 1% below nominal V_out, whereupon power save mode is exited and the converter returns to PWM mode.

These control methods reduce the quiescent current typically to 12 μA per converter and the switching frequency to a minimum achieving the highest converter efficiency. PFM mode operates with very low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor; increasing capacitor values makes the output ripple tend to zero.

8.3.2 Enable

The DC-DC converters and the LDOs are enabled using external enable pins or enable bits with the I²C compatible interface. The signal of the enable pin and the enable bit are logically XORed to generate the enable signal to the converter or LDO. There is one enable pin and one enable bit for each of the LDOs or DCDC converters, which allows start-up of each converter independently. If EN_DCDC1, EN_DCDC2, EN_LDO1, EN_LDO2, ENLDO3, or EN_LDO4 are set to high, the corresponding converter starts up with soft start as previously described. The converters and LDOs can also be enabled by setting the enable bits for each of the LDOs or DCDC converters in register REG_CTRL. See the register description for more details.

Disabling the DC-DC converter or LDO forces the device into shutdown with a shutdown quiescent current as defined in Electrical Characteristics. In this mode, the P- and N-Channel MOSFETs are turned off, and the entire internal control circuitry is switched off. For proper operation the enable pins must be terminated and must not be left floating.

8.3.3 Discharge

The TPS65055 contains a comparator that supervises a voltage applied to the threshold pin and drives a open-drain NMOS according to the input level applied at threshold. If the input voltage at the threshold pin is lower than 1 V, the open-drain NMOS at the discharge output is turned on, pulling the pin to GND. This circuitry is functional as soon as the supply voltage at Vcc exceeds the undervoltage lockout threshold. Therefore the TPS65055 has a shutdown current (all DC-DC converters and LDOs are off) of 9 μA to supply bandgap and comparator.

8.3.4 RST and DPD

The TPS65055 contains two open-drain outputs that are controlled by the I²C compatible interface. The RST and DPD outputs are low (internal NMOS active) per default, once the undervoltage lockout threshold has been exceeded. The status of these outputs can be changed using the REG_CTRL register. See Register Maps for more details.

8.3.5 Short-Circuit Protection

All outputs are short-circuit protected with a maximum output current as defined in Electrical Characteristics.

8.3.6 Thermal Shutdown

As soon as the junction temperature, T_J, exceeds typically 150°C for the DC-DC converters, the device goes into thermal shutdown. In this mode, the P- and N-Channel MOSFETs are turned off. The device continues its operation when the junction temperature falls below the thermal shutdown hysteresis again. A thermal shutdown for one of the DC-DC converters disables both converters simultaneously.

The thermal shutdown temperature for the LDOs are set to typically 140°C. Therefore, a LDO which may be used to power an external voltage never heats up the device that high to turn off the DC-DC converters. If one LDO exceeds the thermal shutdown temperature, all LDOs turn off simultaneously.

8.3.7 LDO1 to LDO4

The low dropout voltage regulators are designed to operate well with low value ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 280 mV at rated output current. Each LDO supports a current limit feature. The LDOs are enabled by the EN_LDO1, ENLDO2, EN_LDO3, and EN_LDO4 pin EXOR with a bit in register REG_CTRL (Reg#02h).

8.5.1 Interface Specification

Table 4. PGOODZ. Register Address: 01h (read only)

PGOODZ	B7	B6	B5	B4	B3	B2	B1	BO
Bit name and function	discharge	DVM	PGOODZ VDCDC1	PGOODZ VDCDC2	PGOODZ LDO1	PGOODZ LDO2	PGOODZ LDO3	PGOODZ LDO4
Set by signal			PGOODZ VDCDC1	PGOODZ VDCDC2	PGOODZ LDO1	PGOODZ LDO2	PGOODZ LDO3	PGOODZ LDO4
Default value loaded by:			PGOOD VDCDC1	PGOOD VDCDC2	PGOOD LDO1	PGOOD LDO2	PGOOD LDO3	PGOOD LDO4
Read/write	R	R	R	R	R	R	R	R

Bit 7	discharge: 0 = Indicates that the comparator input voltage is below the 1 V threshold. 1 = Indicates that the comparator input voltage is above the 1 V threshold.
Bit 6	DVM: 0 = Indicates that the voltage of DCDC2 is not changing. 1 = Indicates that a voltage change of DCDC2 is ongoing.
Bit 5	PGOODZ VDCDC1: 0 = Indicates that the VDCDC1 converter output voltage is within its nominal range. 1 = Indicates that the VDCDC1 converter output voltage is below its target regulation voltage or is disabled.
Bit 4	PGOODZ VDCDC2: 0 = Indicates that the VDCDC2 converter output voltage is within its nominal range. 1 = Indicates that the VDCDC2 converter output voltage is below its target regulation voltage or is disabled.
Bit 3	PGOODZ LDO1: 0 = Indicates that the LDO1 output voltage is within its nominal range. 1 = Indicates that the LDO1 output voltage is below its target regulation voltage or is disabled.
Bit 2	PGOODZ LDO2: 0 = Indicates that the LDO2 output voltage is within its nominal range. 1 = Indicates that LDO2 output voltage is below its target regulation voltage or is disabled.
Bit 1	PGOODZ LDO3: 0 = Indicates that the LDO3 output voltage is within its nominal range. 1 = Indicates that the LDO3 output voltage is below its target regulation voltage or is disabled.
Bit 0	PGOODZ LDO4: 0 = Indicates that the LDO4 output voltage is within its nominal range. 1 = Indicates that the LDO4 output voltage is below its target regulation voltage or is disabled.

Table 5. REG_CTRL. Register Address: 02h (read/write)  Default Value: 00h

REG_CTRL	B7	B6	B5	B4	B3	B2	B1	BO
Bit name and function	RST	DPD	DCDC1 ENABLE	DCDC2 ENABLE	LDO1 ENABLE	LDO2 ENABLE	LDO3 ENABLE	LDO4 ENABLE
Default	0	0	0	0	0	0	0	0
Set by signal
Default value loaded by:	UVLO	UVLO	UVLO	UVLO	UVLO	UVLO	UVLO	UVLO
Read/write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W

The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low output voltage ripple is vital.

The CON_CTRL2 register can be used to take control of the inductive converters.

 

The output voltage for DCDC2 is switched between the value defined in DEFDCDC2_LOW and DEFDCDC2_HIGH depending on the status of the DEFDCDC2 pin. IF DEFDCDC2 is low, the value in DEFDCDC2_LOW is selected, if DEFDCDC2 = high, the value in DEFDCDC2_HIGH is selected.

The LDO_CTRLx registers can be used to set the output voltages of LDO1 to LDO4. The default value is loaded at power-up depending on the status of the DEFLDO pins. See Default Voltage Setting for LDOs and DCDC1 for details. The status of the DEFLDO pins is latched after the undervoltage lockout threshold is exceeded, so the voltage can be changed by reprogramming the register content.

The default value is loaded at power-up depending on the status of the DEFLDO pins. See Default Voltage Setting for LDOs and DCDC1 for details. The status of the DEFLDO pins is latched after the undervoltage lockout threshold is exceeded, so the voltage can be changed by reprogramming the register content.

Per default the DCDC1 converter is internally adjustable and the default output voltage for DCDC1 (bits B0 to B5) depends on the status of the DEFLDO pins – see Default Voltage Setting for LDOs and DCDC1. The status of the DEFLDO pins is latched after the undervoltage lockout threshold is exceeded, so the voltage can be changed by reprogramming the register content.

DCDC1 voltage is listed in Table 16.