11.2.3.2.3 DEEP SLEEP Mode

Entry into DEEP SLEEP mode is controlled by Prima by writing to register CON_CTRL2 of TPS6507x. Before entering DEEP SLEEP mode, Prima will back up all memory and set Bit DS_RDY=1 to indicate the memory was saved and the content is valid. Setting PWR_DS=1 will turn off all voltage rails except DCDC2 for the memory voltage and the PMU will apply a reset signal by pulling PGOOD=LOW. Prima can not detect logic level change by PB_OUT going low in DEEP SLEEP mode. A wakeup from DEEP sleep is therefore managed by the PMU. The PMU will clear Bit PWR_DS and turn on the converters again based on a user “keypress” when PB_IN is being pulled LOW. Prima will now check if DS_RDY=1 to determine if the memory content is still valid and clear the Bit afterwards. In case there is a power loss and the voltage of the PMU is dropping below the undervoltage lockout threshold, the registers in the PMU are re-set to the default and DS_RDY is cleared. The PMU would perform a start-up from OFF state instead of exit from DEEP SLEEP and Sirf PRIMA would read DS_RDY=0, which indicates memory data is not valid.

See Sequence diagrams for Sirf Prima SLEEP and DEEP SLEEP in Figure 54 and Figure 55.

Figure 55. Sequence for Sirf Prima DEEP SLEEP Mode