Figure 7-27 Emergency Shutdown Sequence

When V_SYS crosses below V_{SYS_UVLO_5V}, all Power Good pins will be deasserted, and after 444 ns (nominal) of delay all VRs will shut down. Upon shutdown, all internal discharge resistors are set to 100 Ω to ensure timely decay of all VR outputs. Other conditions that will cause emergency shutdown are the die temperature rising above the critical temperature threshold (T_CRIT), deassertion of Power Good of any rail (configurable), or failure of any rail to reach power good within 10 ms of being enabled (configurable). If PMIC was shutdown by UVLO, it will wait until VSYS rises above V_{SYS_UVLO_5V} + V_{SYS_UVLO_5V_HYS} before reloading the default OTP and checking the state of the CTLx pins. If PMIC was shutdown by temperature, it will wait until temperature drops below T_CRIT – T_{CRIT_HYS} before reloading OTP and checking the state of the CTLx pins. If the PMIC was shutdown by power fault, it will reload OTP after disabling all rails and check the state of the CTLx pins once OTP has finished reloading.