For a detailed description regarding layout recommendations, refer to the TPS65086x Design Guide and to the TPS65086x Schematic and Layout Checklist. For all switching power supplies, the layout is an important step in the design, especially at high peak currents and high switching frequencies. If the layout is not carefully done, the regulator can have stability problems and EMI issues. Therefore, use wide and short traces for the main current path and for the power ground tracks. The input capacitors, output capacitors, and inductors must be placed as close as possible to the device. Use a common-ground node for power ground and use a different, isolated node for control ground to minimize the effects of ground noise. Connect these ground nodes close to the AGND pin by one or two vias. Use of the design guide is highly encouraged in addition to the following list of other basic requirements:

• Do not allow the AGND, PGNDSNSx, or FBGND2 to connect to the thermal pad on the top layer.
• To ensure proper sensing based on FET R_DSON, PGNDSNSx must not connect to PGND until very close to the PGND pin of the FET.
• All inductors, input and output capacitors, and FETs for the converters and controller must be on the same board layer as the IC.
• To achieve the best regulation performance, place feedback connection points near the output capacitors and minimize the control feedback loop as much as possible.
• Bootstrap capacitors must be placed close to the device.
• The internal reference regulators must have their input and output capacitors placed close to the device pins.
• Route DRVHx and SWx as a differential pair. Ensure that there is a PGND path routed in parallel with DRVLx, which provides optimal driver loops.