BUCK1–BUCK6 support dynamic voltage scaling (DVS) for maximum system efficiency. The VR outputs can slew up and down in 25-mV steps for the converters, and either 10-mV or 25-mV steps for the controllers, using the 7-bit voltage ID (VID) defined in Section 6.7 and Section 6.8. DVS slew rate is minimum 2.5 mV/µs. In order to meet the minimum slew rate, VID progresses to the next code at 3-µs (nom) interval per 10-mV or at 6-µs interval per 25-mV steps. When DVS is active, the VR is forced into PWM mode, unless BUCKx_DECAY = 1, to ensure the output keeps track of VID code with minimal delay. Additionally, PGOOD is masked when DVS is in progress. Figure 7-19 shows an example of slew down and up from one VID to another (step size of
10 mV).

Figure 7-19 DVS Timing Diagram I (BUCKx_DECAY = 0)

As shown in Figure 7-20, if a BUCKx_VID[6:0] is set to 7b000 0000, its output voltage will slew down to 0.5 V first, and then will drift down to 0 V as the SMPS stops switching. Subsequently, if a BUCKx_VID[6:0] is set to a value (neither 7b000 0000 nor 7b000 0001) when its output voltage is less than 0.5 V, the VR will ramp up to 0.5 V first with soft-start kicking in, then will slew up to target voltage in the slew rate mentioned previously. It must be noted that a fixed 200 µs of soft-start time is reserved for V_OUT to reach 0.5 V. In this case, however, the SMPS is not forced into PWM mode as it otherwise could cause V_OUT to droop momentarily if V_OUT might have been drifting above 0.5 V for any reason.

Figure 7-20 DVS Timing Diagram II (BUCKx_DECAY = 0)