ZHCSG44F June   2017  – October 2024 TPS650864

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Total Current Consumption
    6. 6.6  Electrical Characteristics: Reference and Monitoring System
    7. 6.7  Electrical Characteristics: Buck Controllers
    8. 6.8  Electrical Characteristics: Synchronous Buck Converters
    9. 6.9  Electrical Characteristics: LDOs
    10. 6.10 Electrical Characteristics: Load Switches
    11. 6.11 Digital Signals: I2C Interface
    12. 6.12 Digital Input Signals (CTLx)
    13. 6.13 Digital Output Signals (IRQB, GPOx)
    14. 6.14 Timing Requirements
    15. 6.15 Switching Characteristics
    16. 6.16 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1  Overview
    2. 7.2  Functional Block Diagram
    3. 7.3  TPS6508640 Design and Settings
      1. 7.3.1 TPS6508640 OTP Summary
    4. 7.4  TPS65086401 Design and Settings
      1. 7.4.1 TPS65086401 OTP Summary
      2.      31
    5. 7.5  TPS6508641 Design and Settings
      1. 7.5.1 TPS6508641 OTP Summary
    6. 7.6  TPS65086470 Design and Settings
      1. 7.6.1 TPS65086470 OTP Summary
    7. 7.7  SMPS Voltage Regulators
      1. 7.7.1 Controller Overview
      2. 7.7.2 Converter Overview
      3. 7.7.3 DVS
      4. 7.7.4 Decay
      5. 7.7.5 Current Limit
    8. 7.8  LDOs and Load Switches
      1. 7.8.1 VTT LDO
      2. 7.8.2 LDOA1–LDOA3
      3. 7.8.3 Load Switches
    9. 7.9  Power Goods (PGOOD or PG) and GPOs
    10. 7.10 Power Sequencing and VR Control
      1. 7.10.1 CTLx Sequencing
      2. 7.10.2 PG Sequencing
      3. 7.10.3 Enable Delay
      4. 7.10.4 Power-Up Sequence
      5. 7.10.5 Power-Down Sequence
      6. 7.10.6 Sleep State Entry and Exit
      7. 7.10.7 Emergency Shutdown
    11. 7.11 Device Functional Modes
      1. 7.11.1 Off Mode
      2. 7.11.2 Standby Mode
      3. 7.11.3 Active Mode
    12. 7.12 I2C Interface
      1. 7.12.1 F/S-Mode Protocol
    13. 7.13 Register Maps
      1. 7.13.1  Register Map Summary
      2. 7.13.2  DEVICEID1: 1st PMIC Device and Revision ID Register (offset = 00h) [reset = X]
      3. 7.13.3  DEVICEID2: 2nd PMIC Device and Revision ID Register (offset = 01h) [reset = X]
      4. 7.13.4  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
      5. 7.13.5  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
      6. 7.13.6  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
      7. 7.13.7  SHUTDNSRC: PMIC Shut-Down Event Register (offset = 05h) [reset = 0000 0000]
      8. 7.13.8  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = X]
      9. 7.13.9  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = X]
      10. 7.13.10 BUCK3DECAY: BUCK3 Decay Control Register (offset = 22h) [reset = X]
      11. 7.13.11 BUCK3VID: BUCK3 VID Register (offset = 23h) [reset = X]
      12. 7.13.12 BUCK3SLPCTRL: BUCK3 Sleep Control VID Register (offset = 24h) [reset = X]
      13. 7.13.13 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = X]
      14. 7.13.14 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = X]
      15. 7.13.15 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = X]
      16. 7.13.16 LDOA2CTRL: LDOA2 Control Register (offset = 28h) [reset = X]
      17. 7.13.17 LDOA3CTRL: LDOA3 Control Register (offset = 29h) [reset = X]
      18. 7.13.18 DISCHCTRL1: 1st Discharge Control Register (offset = 40h) [reset = X]
      19. 7.13.19 DISCHCTRL2: 2nd Discharge Control Register (offset = 41h) [reset = X]
      20. 7.13.20 DISCHCTRL3: 3rd Discharge Control Register (offset = 42h) [reset = X]
      21. 7.13.21 PG_DELAY1: 1st Power Good Delay Register (offset = 43h) [reset = X]
      22. 7.13.22 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      23. 7.13.23 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = X]
      24. 7.13.24 BUCK2SLPCTRL: BUCK2 Sleep Control Register (offset = 93h) [reset = X]
      25. 7.13.25 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = X]
      26. 7.13.26 BUCK4SLPVID: BUCK4 Sleep VID Register (offset = 95h) [reset = X]
      27. 7.13.27 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = X]
      28. 7.13.28 BUCK5SLPVID: BUCK5 Sleep VID Register (offset = 97h) [reset = X]
      29. 7.13.29 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = X]
      30. 7.13.30 BUCK6SLPVID: BUCK6 Sleep VID Register (offset = 99h) [reset = X]
      31. 7.13.31 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = X]
      32. 7.13.32 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = X]
      33. 7.13.33 BUCK123CTRL: BUCK1-3 Control Register (offset = 9Ch) [reset = X]
      34. 7.13.34 PG_DELAY2: 2nd Power Good Delay Register (offset = 9Dh) [reset = X]
      35. 7.13.35 SWVTT_DIS: SWVTT Disable Register (offset = 9Fh) [reset = X]
      36. 7.13.36 I2C_RAIL_EN1: 1st VR Pin Enable Override Register (offset = A0h) [reset = X]
      37. 7.13.37 I2C_RAIL_EN2/GPOCTRL: 2nd VR Pin Enable Override and GPO Control Register (offset = A1h) [reset = X]
      38. 7.13.38 PWR_FAULT_MASK1: 1st VR Power Fault Mask Register (offset = A2h) [reset = X]
      39. 7.13.39 PWR_FAULT_MASK2: 2nd VR Power Fault Mask Register (offset = A3h) [reset = X]
      40. 7.13.40 GPO1PG_CTRL1: 1st GPO1 PG Control Register (offset = A4h) [reset = X]
      41. 7.13.41 GPO1PG_CTRL2: 2nd GPO1 PG Control Register (offset = A5h) [reset = X]
      42. 7.13.42 GPO4PG_CTRL1: 1st GPO4 PG Control Register (offset = A6h) [reset = X]
      43. 7.13.43 GPO4PG_CTRL2: 2nd GPO4 PG Control Register (offset = A7h) [reset = X]
      44. 7.13.44 GPO2PG_CTRL1: 1st GPO2 PG Control Register (offset = A8h) [reset = X]
      45. 7.13.45 GPO2PG_CTRL2: 2nd GPO2 PG Control Register (offset = A9h) [reset = X]
      46. 7.13.46 GPO3PG_CTRL1: 1st GPO3 PG Control Register (offset = AAh) [reset = X]
      47. 7.13.47 GPO3PG_CTRL2: 2nd GPO3 PG Control Register (offset = ABh) [reset = X]
      48. 7.13.48 MISCSYSPG Register (offset = ACh) [reset = X]
        1. 7.13.48.1 VTT_DISCH_CTRL Register (offset = ADh) [reset = X]
      49. 7.13.49 LDOA1_SWB2_CTRL: LDOA1 and SWB2 Control Register (offset = AEh) [reset = X]
      50. 7.13.50 PG_STATUS1: 1st Power Good Status Register (offset = B0h) [reset = 0000 0000]
      51. 7.13.51 PG_STATUS2: 2nd Power Good Status Register (offset = B1h) [reset = 0000 0000]
      52. 7.13.52 PWR_FAULT_STATUS1: 1st Power Fault Status Register (offset = B2h) [reset = 0000 0000]
      53. 7.13.53 PWR_FAULT_STATUS2: 2nd Power Fault Status Register (offset = B3h) [reset = 0000 0000]
      54. 7.13.54 TEMPCRIT: Temperature Fault Status Register (offset = B4h) [reset = 0000 0000]
      55. 7.13.55 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
      56. 7.13.56 OC_STATUS: Overcurrent Fault Status Register (offset = B6h) [reset = 0000 0000]
  9. 8 Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Controller Design Procedure
          1. 8.2.2.1.1 Selecting the Inductor
          2. 8.2.2.1.2 Selecting the Output Capacitors
          3. 8.2.2.1.3 Selecting the FETs
          4. 8.2.2.1.4 Bootstrap Capacitor
          5. 8.2.2.1.5 Setting the Current Limit
          6. 8.2.2.1.6 Selecting the Input Capacitors
        2. 8.2.2.2 Converter Design Procedure
          1. 8.2.2.2.1 Selecting the Inductor
          2. 8.2.2.2.2 Selecting the Output Capacitors
          3. 8.2.2.2.3 Selecting the Input Capacitors
        3. 8.2.2.3 LDO Design Procedure
      3. 8.2.3 Application Curves
      4. 8.2.4 Layout
        1. 8.2.4.1 Layout Guidelines
        2. 8.2.4.2 Layout Example
      5. 8.2.5 VIN 5-V Application
        1. 8.2.5.1 Design Requirements
        2. 8.2.5.2 Design Procedure
        3. 8.2.5.3 Application Curves
    3. 8.3 Power Supply Coupling and Bulk Capacitors
    4. 8.4 Do's and Don'ts
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 9.1.2 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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7.13.23 BUCK1SLPCTRL: BUCK1 Sleep Control Register (offset = 92h) [reset = X]

Figure 7-55 BUCK1SLPCTRL Register
Bit76543210
Bit NameBUCK1_
SLP_ VID[6]		BUCK1_
SLP_ VID[5]		BUCK1_
SLP_ VID[4]		BUCK1_
SLP_ VID[3]		BUCK1_
SLP_ VID[2]		BUCK1_
SLP_ VID[1]		BUCK1_
SLP_ VID[0]		BUCK1_
SLP_ EN
TPS650864011101000
TPS6508640101110000
TPS650864100000010
TPS6508647001111000
AccessR/WR/WR/WR/WR/WR/WR/WR/W
Table 7-49 BUCK1SLPCTRL Register Descriptions
BitFieldTypeResetDescription
7:1BUCK1_SLP_VID[6:0]R/WXThis field sets the BUCK1 regulator output regulation voltage in sleep mode.
See Table 7-22 and Table 7-23 for 10-mV and 25-mV step ranges for VOUT options.
0BUCK1_SLP_ENR/WXBUCK1 sleep mode enable. BUCK1 is factory configured to switch to sleep mode voltage either by CTL3/SLPENB1 pin or by CTL6/SLPENB2 pin.
0: Disable. Uses BUCK1_VID in all cases.
1: Enabled. Uses BUCK1_SLP_VID when assigned sleep pin is low.
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