ZHCSFJ2E September   2015  – October 2024 TPS65094

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Options
    1. 4.1 OTP Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Total Current Consumption
    6. 6.6  Electrical Characteristics: Reference and Monitoring System
    7. 6.7  Electrical Characteristics: Buck Controllers
    8. 6.8  Electrical Characteristics: Synchronous Buck Converters
    9. 6.9  Electrical Characteristics: LDOs
    10. 6.10 Electrical Characteristics: Load Switches
    11. 6.11 Digital Signals: I2C Interface
    12. 6.12 Digital Input Signals (LDOLS_EN, SWA1_EN, THERMTRIPB, PMICEN, SLP_S3B, SLP_S4B, SLP_S0B)
    13. 6.13 Digital Output Signals (IRQB, RSMRSTB, PCH_PWROK, PROCHOT)
    14. 6.14 Timing Requirements
    15. 6.15 Switching Characteristics
    16. 6.16 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Good (PGOOD)
      2. 7.3.2 Register Reset Conditions
      3. 7.3.3 SMPS Voltage Regulators
        1. 7.3.3.1 Controller Overview
        2. 7.3.3.2 Converter Overview
        3. 7.3.3.3 DVS
        4. 7.3.3.4 Current Limit
      4. 7.3.4 LDOs and Load Switches
        1. 7.3.4.1 VTT LDO
        2. 7.3.4.2 LDOA1–LDOA3
        3. 7.3.4.3 Load Switches
      5. 7.3.5 Power Sequencing and VR Control
        1. 7.3.5.1 Cold Boot
        2. 7.3.5.2 Cold OFF
        3. 7.3.5.3 Connected Standby Entry and Exit
        4. 7.3.5.4 S0 to S3 Entry and Exit
        5. 7.3.5.5 S0 to S4/5 Entry and Exit
        6. 7.3.5.6 Emergency Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 F/S-Mode Protocol
    6. 7.6 Register Maps
      1. 7.6.1  55
      2. 7.6.2  VENDORID: PMIC Vendor ID Register (offset = 00h) [reset = 0010 0010]
      3. 7.6.3  DEVICEID: PMIC Device and Revision ID Register (offset = 01h) [reset = OTP Dependent]
      4. 7.6.4  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
      5. 7.6.5  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
      6. 7.6.6  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
      7. 7.6.7  OFFONSRC: PMIC Power Transition Event Register (offset = 05h) [reset = 0000 0000]
      8. 7.6.8  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = 0011 1000]
      9. 7.6.9  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 0000 0000]
      10. 7.6.10 BUCK3CTRL: BUCK3 Control Register (offset = 23h) [reset = 0001 0001]
      11. 7.6.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP Dependent]
      12. 7.6.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP Dependent]
      13. 7.6.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = 0011 1101]
      14. 7.6.14 DISCHCNT1: Discharge Control1 Register (offset = 40h) [reset = 0101 0101]
      15. 7.6.15 DISCHCNT2: Discharge Control2 Register (offset = 41h) [reset = 0101 0101]
      16. 7.6.16 DISCHCNT3: Discharge Control3 Register (offset = 42h) [reset = 0000 0101]
      17. 7.6.17 POK_DELAY: PCH_PWROK Delay Register (offset = 43h) [reset = 0000 0111]
      18. 7.6.18 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      19. 7.6.19 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 0010 1111]
      20. 7.6.20 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 0100 1011]
      21. 7.6.21 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP Dependent]
      22. 7.6.22 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP Dependent]
      23. 7.6.23 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP Dependent]
      24. 7.6.24 VR_CTRL1: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP Dependent]
      25. 7.6.25 VR_CTRL2: VR Enable Register (offset = 9Eh) [reset = 0000 0000]
      26. 7.6.26 VR_CTRL3: VR Enable/Disable Register (offset = 9Fh) [reset = OTP Dependent]
      27. 7.6.27 GPO_CTRL: GPO Control Register (offset = A1h) [reset = 0010 0000]
      28. 7.6.28 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = 1100 0000]
      29. 7.6.29 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 0011 0111]
      30. 7.6.30 DISCHCNT4: Discharge Control4 Register (offset = ADh) [reset = 0110 0001]
      31. 7.6.31 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP Dependent]
      32. 7.6.32 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
      33. 7.6.33 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
        1. 7.6.33.1 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
        2. 7.6.33.2 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
      34. 7.6.34 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Controller Design Procedure
          1. 8.1.2.1.1 Selecting the Output Capacitors
          2. 8.1.2.1.2 Selecting the Inductor
          3. 8.1.2.1.3 Selecting the FETs
          4. 8.1.2.1.4 Bootstrap Capacitor
          5. 8.1.2.1.5 Selecting the Input Capacitors
            1. 8.1.2.1.5.1 Setting the Current Limit
        2. 8.1.2.2 Converter Design Procedure
          1. 8.1.2.2.1 Selecting the Inductor
          2. 8.1.2.2.2 Selecting the Output Capacitors
          3. 8.1.2.2.3 Selecting the Input Capacitors
        3. 8.1.2.3 LDO Design Procedure
      3. 8.1.3 Application Curves
    2. 8.2 Specific Application for TPS650944
    3. 8.3 Dos and Don'ts
    4.     Power Supply Recommendations
    5. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.3.3 SMPS Voltage Regulators

The buck controllers integrate gate drivers for external power stages with programmable current limit (set by an external resistor at ILIMx pin), which allows for optimal selection of external passive components based on the desired system load. The buck converters include integrated power stage and require a minimum number of pins for power input, inductor, and output voltage feedback input. Combined with high-frequency switching, all these features allow use of inductors in small form factor, thus reducing the total cost and size of the system.

BUCK3–BUCK6 have selectable auto- and forced-PWM mode through the BUCKx_MODE bit in the BUCKxCTRL register. In default auto mode, the VR automatically switches between PWM and PFM depending on the output load to maximize efficiency. The host cannot select Forced PWM mode for other SMPS VRs as they stay in auto mode at all times.

See Table 7-3 and Table 7-4 for the full voltage tables for all SMPS regulators.

Table 7-3 10-mV Step-Size VOUT Range (BUCK1, BUCK2, BUCK5, BUCK6)
VID BitsVOUTVID BitsVOUTVID BitsVOUT
0000000001010110.9210101101.35
00000010.5001011000.9310101111.36
00000100.5101011010.9410110001.37
00000110.5201011100.9510110011.38
00001000.5301011110.9610110101.39
00001010.5401100000.9710110111.40
00001100.5501100010.9810111001.41
00001110.5601100100.9910111011.42
00010000.5701100111.0010111101.43
00010010.5801101001.0110111111.44
00010100.5901101011.0211000001.45
00010110.6001101101.0311000011.46
00011000.6101101111.0411000101.47
00011010.6201110001.0511000111.48
00011100.6301110011.0611001001.49
00011110.6401110101.0711001011.50
00100000.6501110111.0811001101.51
00100010.6601111001.0911001111.52
00100100.6701111011.1011010001.53
00100110.6801111101.1111010011.54
00101000.6901111111.1211010101.55
00101010.7010000001.1311010111.56
00101100.7110000011.1411011001.57
00101110.7210000101.1511011011.58
00110000.7310000111.1611011101.59
00110010.7410001001.1711011111.60
00110100.7510001011.1811100001.61
00110110.7610001101.1911100011.62
00111000.7710001111.2011100101.63
00111010.7810010001.2111100111.64
00111100.7910010011.2211101001.65
00111110.8010010101.2311101011.66
01000000.8110010111.2411101101.67
01000010.8210011001.2511101111.67
01000100.8310011011.2611110001.67
01000110.8410011101.2711110011.67
01001000.8510011111.2811110101.67
01001010.8610100001.2911110111.67
01001100.8710100011.3011111001.67
01001110.8810100101.3111111011.67
01010000.8910100111.3211111101.67
01010010.9010101001.3311111111.67
01010100.9110101011.34
Table 7-4 25-mV Step-Size VOUT Range (BUCK3, BUCK4)
VID BitsVOUTVID BitsVOUTVID BitsVOUT
0000000001010111.70010101102.775
00000010.65001011001.72510101112.800
00000100.67501011011.75010110002.825
00000110.70001011101.77510110012.850
00001000.72501011111.80010110102.875
00001010.75001100001.82510110112.900
00001100.77501100011.85010111002.925
00001110.80001100101.87510111012.950
00010000.82501100111.90010111102.975
00010010.85001101001.92510111113.000
00010100.87501101011.95011000003.025
00010110.90001101101.97511000013.050
00011000.92501101112.00011000103.075
00011010.95001110002.02511000113.100
00011100.97501110012.05011001003.125
00011111.00001110102.07511001013.150
00100001.02501110112.10011001103.175
00100011.05001111002.12511001113.200
00100101.07501111012.15011010003.225
00100111.10001111102.17511010013.250
00101001.12501111112.20011010103.275
00101011.15010000002.22511010113.300
00101101.17510000012.25011011003.325
00101111.20010000102.27511011013.350
00110001.22510000112.30011011103.375
00110011.25010001002.32511011113.400
00110101.27510001012.35011100003.425
00110111.30010001102.37511100013.450
00111001.32510001112.40011100103.475
00111011.35010010002.42511100113.500
00111101.37510010012.45011101003.525
00111111.40010010102.47511101013.550
01000001.42510010112.50011101103.575
01000011.45010011002.52511101113.575
01000101.47510011012.55011110003.575
01000111.50010011102.57511110013.575
01001001.52510011112.60011110103.575
01001011.55010100002.62511110113.575
01001101.57510100012.65011111003.575
01001111.60010100102.67511111013.575
01010001.62510100112.70011111103.575
01010011.65010101002.72511111113.575
01010101.67510101012.750
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