ZHCSFJ2E September   2015  – October 2024 TPS65094

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Options
    1. 4.1 OTP Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Total Current Consumption
    6. 6.6  Electrical Characteristics: Reference and Monitoring System
    7. 6.7  Electrical Characteristics: Buck Controllers
    8. 6.8  Electrical Characteristics: Synchronous Buck Converters
    9. 6.9  Electrical Characteristics: LDOs
    10. 6.10 Electrical Characteristics: Load Switches
    11. 6.11 Digital Signals: I2C Interface
    12. 6.12 Digital Input Signals (LDOLS_EN, SWA1_EN, THERMTRIPB, PMICEN, SLP_S3B, SLP_S4B, SLP_S0B)
    13. 6.13 Digital Output Signals (IRQB, RSMRSTB, PCH_PWROK, PROCHOT)
    14. 6.14 Timing Requirements
    15. 6.15 Switching Characteristics
    16. 6.16 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Good (PGOOD)
      2. 7.3.2 Register Reset Conditions
      3. 7.3.3 SMPS Voltage Regulators
        1. 7.3.3.1 Controller Overview
        2. 7.3.3.2 Converter Overview
        3. 7.3.3.3 DVS
        4. 7.3.3.4 Current Limit
      4. 7.3.4 LDOs and Load Switches
        1. 7.3.4.1 VTT LDO
        2. 7.3.4.2 LDOA1–LDOA3
        3. 7.3.4.3 Load Switches
      5. 7.3.5 Power Sequencing and VR Control
        1. 7.3.5.1 Cold Boot
        2. 7.3.5.2 Cold OFF
        3. 7.3.5.3 Connected Standby Entry and Exit
        4. 7.3.5.4 S0 to S3 Entry and Exit
        5. 7.3.5.5 S0 to S4/5 Entry and Exit
        6. 7.3.5.6 Emergency Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Off Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
    5. 7.5 Programming
      1. 7.5.1 I2C Interface
        1. 7.5.1.1 F/S-Mode Protocol
    6. 7.6 Register Maps
      1. 7.6.1  55
      2. 7.6.2  VENDORID: PMIC Vendor ID Register (offset = 00h) [reset = 0010 0010]
      3. 7.6.3  DEVICEID: PMIC Device and Revision ID Register (offset = 01h) [reset = OTP Dependent]
      4. 7.6.4  IRQ: PMIC Interrupt Register (offset = 02h) [reset = 0000 0000]
      5. 7.6.5  IRQ_MASK: PMIC Interrupt Mask Register (offset = 03h) [reset = 1111 1111]
      6. 7.6.6  PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000]
      7. 7.6.7  OFFONSRC: PMIC Power Transition Event Register (offset = 05h) [reset = 0000 0000]
      8. 7.6.8  BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = 0011 1000]
      9. 7.6.9  BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 0000 0000]
      10. 7.6.10 BUCK3CTRL: BUCK3 Control Register (offset = 23h) [reset = 0001 0001]
      11. 7.6.11 BUCK4CTRL: BUCK4 Control Register (offset = 25h) [reset = OTP Dependent]
      12. 7.6.12 BUCK5CTRL: BUCK5 Control Register (offset = 26h) [reset = OTP Dependent]
      13. 7.6.13 BUCK6CTRL: BUCK6 Control Register (offset = 27h) [reset = 0011 1101]
      14. 7.6.14 DISCHCNT1: Discharge Control1 Register (offset = 40h) [reset = 0101 0101]
      15. 7.6.15 DISCHCNT2: Discharge Control2 Register (offset = 41h) [reset = 0101 0101]
      16. 7.6.16 DISCHCNT3: Discharge Control3 Register (offset = 42h) [reset = 0000 0101]
      17. 7.6.17 POK_DELAY: PCH_PWROK Delay Register (offset = 43h) [reset = 0000 0111]
      18. 7.6.18 FORCESHUTDN: Force Emergency Shutdown Control Register (offset = 91h) [reset = 0000 0000]
      19. 7.6.19 BUCK4VID: BUCK4 VID Register (offset = 94h) [reset = 0010 1111]
      20. 7.6.20 BUCK5VID: BUCK5 VID Register (offset = 96h) [reset = 0100 1011]
      21. 7.6.21 BUCK6VID: BUCK6 VID Register (offset = 98h) [reset = OTP Dependent]
      22. 7.6.22 LDOA2VID: LDOA2 VID Register (offset = 9Ah) [reset = OTP Dependent]
      23. 7.6.23 LDOA3VID: LDOA3 VID Register (offset = 9Bh) [reset = OTP Dependent]
      24. 7.6.24 VR_CTRL1: BUCK1-3 Control Register (offset = 9Ch) [reset = OTP Dependent]
      25. 7.6.25 VR_CTRL2: VR Enable Register (offset = 9Eh) [reset = 0000 0000]
      26. 7.6.26 VR_CTRL3: VR Enable/Disable Register (offset = 9Fh) [reset = OTP Dependent]
      27. 7.6.27 GPO_CTRL: GPO Control Register (offset = A1h) [reset = 0010 0000]
      28. 7.6.28 PWR_FAULT_MASK1: VR Power Fault Mask1 Register (offset = A2h) [reset = 1100 0000]
      29. 7.6.29 PWR_FAULT_MASK2: VR Power Fault Mask2 Register (offset = A3h) [reset = 0011 0111]
      30. 7.6.30 DISCHCNT4: Discharge Control4 Register (offset = ADh) [reset = 0110 0001]
      31. 7.6.31 LDOA1CTRL: LDOA1 Control Register (offset = AEh) [reset = OTP Dependent]
      32. 7.6.32 PG_STATUS1: Power Good Status1 Register (offset = B0h) [reset = 0000 0000]
      33. 7.6.33 PG_STATUS2: Power Good Status2 Register (offset = B1h) [reset = 0000 0000]
        1. 7.6.33.1 PWR_FAULT_STATUS1: Power Fault Status1 Register (offset = B2h) [reset = 0000 0000]
        2. 7.6.33.2 PWR_FAULT_STATUS2: Power Fault Status2 Register (offset = B3h) [reset = 0000 0000]
      34. 7.6.34 TEMPHOT: Temperature Hot Status Register (offset = B5h) [reset = 0000 0000]
  9. 8 Application and Implementation
    1. 8.1 Typical Application
      1. 8.1.1 Design Requirements
      2. 8.1.2 Detailed Design Procedure
        1. 8.1.2.1 Controller Design Procedure
          1. 8.1.2.1.1 Selecting the Output Capacitors
          2. 8.1.2.1.2 Selecting the Inductor
          3. 8.1.2.1.3 Selecting the FETs
          4. 8.1.2.1.4 Bootstrap Capacitor
          5. 8.1.2.1.5 Selecting the Input Capacitors
            1. 8.1.2.1.5.1 Setting the Current Limit
        2. 8.1.2.2 Converter Design Procedure
          1. 8.1.2.2.1 Selecting the Inductor
          2. 8.1.2.2.2 Selecting the Output Capacitors
          3. 8.1.2.2.3 Selecting the Input Capacitors
        3. 8.1.2.3 LDO Design Procedure
      3. 8.1.3 Application Curves
    2. 8.2 Specific Application for TPS650944
    3. 8.3 Dos and Don'ts
    4.     Power Supply Recommendations
    5. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 接收文档更新通知
    4. 9.4 支持资源
    5. 9.5 Trademarks
    6. 9.6 静电放电警告
    7. 9.7 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

TPS65094 RSK Package 64-Pin VQFN With Thermal Pad Top View
The thermal pad must be connected to the system power ground plane.
RSK Package 64-Pin VQFN With Thermal Pad Top View
Table 5-1 Pin Functions
PIN I/O SUPPLY, OP VOLTAGE LEVEL DESCRIPTION
NO. NAME
SMPS REGULATORS
1 FBGND2 I Remote negative feedback sense for BUCK2 controller. Connect to VCCGI VSS SENSE sent from the SoC to the PMIC.
2 FBVOUT2 I Remote positive feedback sense for BUCK2 controller. Connect to VCCGI VCC SENSE sent from the SoC to the PMIC.
3 DRVH2 O VSYS + 5 V High-side gate driver output for BUCK2 controller
4 SW2 I Switch node connection for BUCK2 controller
5 BOOT2 I VSYS + 5 V Bootstrap pin for BUCK2 controller. Connect a 100-nF ceramic capacitor between this pin and SW2 pin.
6 PGNDSNS2 I Power GND connection for BUCK2. Connect to ground terminal of external low-side FET.
7 DRVL2 O 5 V Low-side gate driver output for BUCK2 controller
8 DRV5V_2_A1 I 5 V 5-V supply to BUCK2 gate driver and LDOA1. Bypass to ground with a 2.2-µF (typical) ceramic capacitor. Shorted on board to LDO5P0 pin.
10 LX3 O Switch node connection for BUCK3 converter. Connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR.
11 PVIN3 I 5 V Power input to BUCK3 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor.
12 FB3 I Remote feedback sense for BUCK3 converter. Connect to positive terminal of output capacitor.
20 LX5 O Switch node connection for BUCK5 converter. Connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR.
21 PVIN5 I 5 V Power input to BUCK5 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor.
22 FB5 I Remote feedback sense for BUCK5 converter. Connect to positive terminal of output capacitor.
23 FB4 I Remote feedback sense for BUCK4 converter. Connect to positive terminal of output capacitor.
24 PVIN4 I 5 V Power input to BUCK4 converter. Bypass to ground with a 10-µF (typical) ceramic capacitor.
25 LX4 O Switch node connection for BUCK4 converter. Connect to a 0.47-µH (typical) inductor with less than 50-mΩ DCR.
29 FBVOUT1 I Remote feedback sense for BUCK1 controller. Connect to VNN VCC SENSE sent from the SoC to the PMIC.
30 ILIM1 I Current limit set pin for BUCK1 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET.
33 DRVH1 O VSYS + 5 V High-side gate driver output for BUCK1 controller
34 SW1 I Switch node connection for BUCK1 controller
35 BOOT1 I VSYS + 5 V Bootstrap pin for BUCK1 controller. Connect a 100-nF ceramic capacitor between this pin and SW1 pin.
36 PGNDSNS1 I Power GND connection for BUCK1. Connect to ground terminal of external low-side FET.
37 DRVL1 O 5 V Low-side gate driver output for BUCK1 controller
38 DRV5V_1_6 I 5 V 5-V supply to BUCK1 and BUCK6 gate drivers. Bypass to ground with a 2.2-µF (typical) ceramic capacitor. Shorted on board to LDO5P0 pin.
39 DRVL6 O 5 V Low-side gate driver output for BUCK6 controller
40 PGNDSNS6 I Power GND connection for BUCK6. Connect to ground terminal of external low-side FET.
41 BOOT6 I VSYS + 5 V Bootstrap pin for BUCK6 controller. Connect a 100-nF ceramic capacitor between this pin and SW6 pin.
42 SW6 I Switch node connection for BUCK6 controller
43 DRVH6 O VSYS + 5 V High-side gate driver output for BUCK6 controller
44 FBVOUT6 I Remote feedback sense for BUCK6 controller. Connect to positive terminal of output capacitor.
45 ILIM6 I Current limit set pin for BUCK6 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET.
64 ILIM2 I Current limit set pin for BUCK2 controller. Fit a resistor from this pin to ground to set current limit of external low-side FET.
LDO and LOAD SWITCHES
9 LDOA1 O 1.35–3.3 V LDOA1 output. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.
17 SWB1 O 0.5–3.3 V
(1.8-V Typical)		 Output of load switch B1. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Short with SWB2.
18 PVINSWB1_B2 I 0.5–3.3 V
(1.8-V Typical)		 Power supply to load switch B1 and B2. Bypass to ground with a 1-µF (typical) ceramic capacitor to improve transient performance. Connect to ground when not in use.
19 SWB2 O 0.5–3.3 V
(1.8-V Typical)		 Output of load switch B2. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Short with SWB1. Leave floating when not in use.
31 SWA1 O 0.5–3.3 V Output of load switch A1. Bypass to ground with a 0.1-µF (typical) ceramic capacitor. Leave floating when not in use.
32 PVINSWA1 I 0.5–3.3 V Power supply to load switch A1. Bypass to ground with a 1-µF (typical) ceramic capacitor to improve transient performance. Connect to ground when not in use.
46 PVINVTT I VDDQ Power supply to VTT LDO. Bypass to ground with a 10-µF (minimum) ceramic capacitor. Connect to ground when not in use.
47 VTT O VDDQ / 2 Output of load VTT LDO. Bypass to ground with 2× 22-µF (minimum) ceramic capacitors. Leave floating when not in use.
48 VTTFB I VDDQ / 2 Remote feedback sense for VTT LDO. Connect to positive terminal of output capacitor. Short to GND when not in use.
49 LDOA3 O 0.7–1.5 V Output of LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.
50 PVINLDOA2_A3 I 1.8 V Power supply to LDOA2 and LDOA3. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Connect to ground when not in use.
51 LDOA2 O 0.7–1.5 V Output of LDOA2. Bypass to ground with a 4.7-µF (typical) ceramic capacitor. Leave floating when not in use.
54 LDO3P3 O 3.3 V Output of 3.3-V internal LDO. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
56 LDO5P0 O 5 V Output of 5-V internal LDO or an internal switch that connects this pin to V5ANA. Bypass to ground with a 4.7-µF (typical) ceramic capacitor.
57 V5ANA I 5 V External 5-V supply input to internal load switch that connects this pin to LDO5P0 pin. Bypass this pin with an optional ceramic capacitor to improve transient performance.
INTERFACE
13 PMICEN I PMIC cold-boot pin. At assertion rising edge of the signal of this pin power state transitions from G3 to S4/S5. Driving the pin to L shuts down all VRs.
14 LDOLS_EN or SWA1_EN I Enable pin for LDOA2, LDOA3, and SWA1 when OTP is configured to LDOLS_EN. Enable pin for just SWA1 when OTP is configured to SWA1_EN. Resources turn on at assertion (H) and turn off at deassertion (L) of the pin. Optionally, when the pin is pulled low, the host can write to enable bits in Reg 0xA0–Reg 0xA1 to control the rails.
15 IRQB O Open-drain output interrupt pin. Refer to Section 7.6.4, IRQ: PMIC Interrupt Register, for definitions.
16 RSMRSTB O Open-drain output Always-ON-rail Power Good. It reflects a valid state whenever VSYS is available.
26 GPO O Open-drain output controlled by an I2C register bit defined in Section 7.6.27, GPO_CTRL: GPO Control Register, by the user, which then can be used as an enable signal to an external VR.
27 PCH_PWROK O Open-drain output global Power Good. It reflects a valid state whenever VSYS is available.
28 PROCHOT O Optional open-drain output for indicating PMIC thermal event. Invert before connecting to SoC if used, otherwise leave floating. This pin is triggered when any of the PMIC die temperature sensors detects the THOT temperature.
58 CLK I I2C clock
59 DATA I/O I2C data
60 THERMTRIPB I Thermal shutdown signal from SoC
61 SLP_S0B I Power state pin. PMIC goes into Connected Standby at falling edge and exits from Connected Standby at rising edge.
62 SLP_S3B I Power state pin. PMIC goes into S3 at falling edge and exits from S3, transitions into S0 at rising edge.
63 SLP_S4B I Power state pin. PMIC goes into S4 at falling edge and exits from S4, transitions into S3 at rising edge.
REFERENCE
53 VREF O 1.25 V Band-gap reference output. Stabilize it by connecting a 100-nF (typical) ceramic capacitor between this pin and quiet ground.
52 AGND — Analog ground. Do not connect to the thermal pad ground on top layer. Connect to ground of VREF capacitor.
55 VSYS I System voltage detection and input to internal LDOs (3.3 V and 5 V). Bypass to ground with a 1-µF (typical) ceramic capacitor.
THERMAL PAD
— Thermal pad — Connect to PCB ground plane using multiple vias for good thermal and electrical performance.
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