SUPPLY CURRENT |
VI |
Input voltage (VIN) |
|
1.8 |
|
6 |
V |
|
Supply current (VIN) |
Device not switching |
|
14 |
25 |
µA |
|
Supply current (SUP) |
Device not switching |
|
1.9 |
3 |
mA |
|
Supply current (VCOM buffer) |
|
|
750 |
1500 |
µA |
VIT– |
Undervoltage lockout threshold (VIN) |
VI falling |
|
1.6 |
1.8 |
V |
VIT+ |
Undervoltage lockout threshold (VIN) |
VI rising |
|
1.7 |
1.9 |
V |
|
Thermal shutdown temperature threshold |
TJ rising |
|
155 |
|
°C |
|
Thermal shutdown temperature hysteresis |
|
|
10 |
|
°C |
LOGIC SIGNALS |
VIH |
High-level input voltage (CTRL) |
|
1.6 |
|
|
V |
VIL |
Low-level input voltage (CTRL) |
|
|
|
0.4 |
V |
IIH, IIL |
Input current (CTRL) |
CTRL = VI or GND |
|
0.01 |
0.2 |
µA |
BOOST CONVERTER |
VO |
Output voltage |
|
|
|
15 |
V |
Vref |
Boost converter reference voltage (FB) |
|
1.136 |
1.146 |
1.154 |
V |
IIB |
Input bias current (FB) |
|
|
10 |
100 |
nA |
rDS(on) |
Drain-source on-state resistance (Q1) |
IDS = 500 mA |
VO = 10 V |
|
200 |
300 |
mΩ |
VO = 5 V |
|
305 |
450 |
rDS(on) |
Drain-source on-state resistance (Q2) |
IDS = 500 mA |
VO = 10 V |
|
8 |
15 |
Ω |
VO = 5 V |
|
12 |
22 |
IDS |
Drain-source current rating (Q2) |
|
1 |
|
|
A |
|
Current limit (SW) |
|
2 |
2.5 |
3.4 |
A |
I(SW)(off) |
Off-state current (SW) |
V(SW) = 15 V |
|
1 |
10 |
µA |
VIT+ |
Overvoltage protection threshold (SUP) |
V(SUP) rising |
16 |
|
20 |
V |
ΔVO(ΔVI) |
Line regulation |
VI = 1.8 V to 5 V |
IO = 1 mA |
|
0.007 |
|
%/V |
ΔVO(ΔIO) |
Load regulation |
VI = 5 V |
IO = 0 A to 400 mA |
|
0.16 |
|
%/A |
VIT+ |
Gate drive threshold (FB)(2) |
|
–12% of Vref |
|
–4% of Vref |
V |
NEGATIVE CHARGE PUMP |
VO |
Output voltage |
|
|
|
–2 |
V |
V(REF) |
Reference output voltage (REF) |
|
1.205 |
1.213 |
1.219 |
V |
Vref |
Feedback regulation voltage (FBN) |
|
–36 |
0 |
36 |
mV |
IIB |
Input bias current (FBN) |
|
|
10 |
100 |
nA |
rDS(on) |
Drain-source on-state resistance (Q4) |
IDS = 20 mA |
|
4.4 |
|
Ω |
V(DRVN) |
Current sink voltage drop(1) |
V(FBN) = 5% above nominal voltage |
I(DRVN) = 50 mA |
|
130 |
300 |
mV |
I(DRVN) = 100 mA |
|
280 |
450 |
ΔVO(ΔIO) |
Load regulation |
VO = –5 V |
IO = 0 mA to 20 mA |
|
0.016 |
|
%/mA |
POSITIVE CHARGE PUMP |
VO |
Output voltage |
CTRL = GND |
VGH = open |
|
|
30 |
V |
Vref |
Feedback regulation voltage (FBP) |
CTRL = GND |
VGH = open |
1.187 |
1.214 |
1.238 |
V |
IIB |
Input bias current (FBP) |
CTRL = GND |
VGH = open |
|
10 |
100 |
nA |
rDS(on) |
Drain-source on-state resistance (Q3) |
IDS = 20 mA |
|
1.1 |
|
Ω |
V(SUP) – V(DRVP) |
Current sink voltage drop(1) |
V(FBP) = 5% below nominal voltage |
I(DRVP) = 50 mA |
|
420 |
650 |
mV |
I(DRVP)= 100 mA |
|
900 |
1400 |
ΔVO(ΔIO) |
Load regulation |
VO = 24 V |
IO = 0 mA to 20 mA |
|
0.07 |
|
%/mA |
GATE-VOLTAGE SHAPING |
rDS(on) |
Drain-source on-state resistance (Q5) |
IO = –20 mA |
|
12 |
30 |
Ω |
I(ADJ) |
Capacitor charge current |
V(ADJ) = 20 V |
V(CPI) = 30 V |
160 |
200 |
240 |
µA |
VOmin |
Minimum output voltage |
V(ADJ) = 0 V |
IO = –10 mA |
|
2 |
|
V |
IOM |
Maximum output current |
|
20 |
|
|
mA |
TIMING CIRCUITS DLY1, DLY2, FDLY |
I(DLY1) |
Drive current into delay capacitor (DLY1) |
V(DLY1) = 1.213 V |
3 |
5 |
7 |
µA |
I(DLY2) |
Drive current into delay capacitor (DLY1) |
V(DLY2) = 1.213 V |
3 |
5 |
7 |
µA |
R(FDLY) |
Fault time delay resistor |
|
250 |
450 |
650 |
kΩ |
GATE DRIVE (GD) |
VOL |
Low-level output voltage (GD) |
IOL = 500 µA |
|
|
0.5 |
V |
IOH |
Off-state current (GD) |
VOH = 15 V |
|
0.001 |
1 |
µA |
VCOM BUFFER |
VISR |
Single-ended input voltage (IN) |
|
2.25 |
|
V(SUP) – 2 V |
V |
VIO |
Input offset voltage (IN) |
IO = 0 mA |
–25 |
|
25 |
mV |
ΔVO(ΔIO) |
Load regulation |
IO = ±25 mA |
–37 |
|
37 |
mV |
IO = ±50 mA |
–77 |
|
55 |
IO = ±100 mA |
–85 |
|
85 |
IO = ±150 mA |
–110 |
|
110 |
IIB |
Input bias current (IN) |
|
–300 |
–30 |
300 |
nA |
IOM |
Maximum output current (VCOM) |
V(SUP) = 15 V |
1.2 |
|
|
A |
V(SUP) = 10 V |
0.65 |
|
|
V(SUP) = 5 V |
0.15 |
|
|