ZHCSF63A September   2013  – June 2016 TPS65154

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3. 1.3 说明
    4. 1.4 简化系统图
  2. 2 修订历史记录
  3. 3 Pin Configuration and Functions
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  Linear Regulator (VCC)
        1. 5.3.1.1 Power-Up (Linear Regulator)
        2. 5.3.1.2 Power-Down (Linear Regulator)
        3. 5.3.1.3 Protection (Linear Regulator)
      2. 5.3.2  Boost Converter 1 (AVDD)
        1. 5.3.2.1 Power-Up (Boost Converter 1)
        2. 5.3.2.2 Power-Down (Boost Converter 1)
        3. 5.3.2.3 Protection (Boost Converter 1)
      3. 5.3.3  Boost Converter 2 (VGH)
        1. 5.3.3.1 Power-Up (Boost Converter 2)
        2. 5.3.3.2 Power-Down (Boost Converter 2)
        3. 5.3.3.3 Protection (Boost Converter 2)
      4. 5.3.4  Negative Charge Pump (VGL)
        1. 5.3.4.1 Power-Up (Negative Charge Pump)
        2. 5.3.4.2 Power-Down (Negative Charge Pump)
        3. 5.3.4.3 Protection (Negative Charge Pump)
      5. 5.3.5  Gate Voltage Shaping
      6. 5.3.6  Panel Discharge (XAO)
      7. 5.3.7  Reset Generator (RST)
      8. 5.3.8  Programmable VCOM
        1. 5.3.8.1 Operational Amplifier Performance
        2. 5.3.8.2 Power-Up (Programmable VCOM)
        3. 5.3.8.3 Power-Down (Programmable VCOM)
      9. 5.3.9  WLED Driver
        1. 5.3.9.1 WLED Boost Converter
        2. 5.3.9.2 Current Sinks
        3. 5.3.9.3 Protection
        4. 5.3.9.4 Enable and Start-Up
      10. 5.3.10 Undervoltage Lockout
    4. 5.4 Device Functional Modes
      1. 5.4.1 Dimming Modes
        1. 5.4.1.1 Direct Dimming
        2. 5.4.1.2 Phase-Shift Dimming
      2. 5.4.2 Power Sequencing
        1. 5.4.2.1 Power-Up
        2. 5.4.2.2 Power-Down
    5. 5.5 Programming
      1. 5.5.1 Configuration
        1. 5.5.1.1 General
          1. 5.5.1.1.1 I2C Interface
          2. 5.5.1.1.2 Slave Addresses
          3. 5.5.1.1.3 Write Protect
      2. 5.5.2 Programming Examples (Excluding VCOM)
        1. 5.5.2.1 Writing to a Single RAM Register
        2. 5.5.2.2 Writing to Multiple RAM Registers
        3. 5.5.2.3 Saving Contents of all RAM Registers to EEPROM
        4. 5.5.2.4 Reading from a Single RAM Register
        5. 5.5.2.5 Reading from a Single EEPROM Register
        6. 5.5.2.6 Reading from Multiple RAM Registers
        7. 5.5.2.7 Reading from Multiple EEPROM Registers
      3. 5.5.3 Programming Examples - VCOM
        1. 5.5.3.1 Writing a VCOM Value of 77h to WR
        2. 5.5.3.2 Writing a VCOM Value of 77h to IVR and WR
        3. 5.5.3.3 Reading a VCOM Value of 77h from WR
        4. 5.5.3.4 Reading a VCOM Value of 77h from IVR
    6. 5.6 Register Map
      1. 5.6.1 Configuration Registers (Excluding VCOM)
        1. 5.6.1.1  CONFIG (00h)
        2. 5.6.1.2  VCC (01h)
        3. 5.6.1.3  DLY1 (02h)
        4. 5.6.1.4  AVDD (03h)
        5. 5.6.1.5  FSW1 (04h)
        6. 5.6.1.6  SS2 (05h)
        7. 5.6.1.7  DLY2 (06h)
        8. 5.6.1.8  VGL (07h)
        9. 5.6.1.9  SS3 (08h)
        10. 5.6.1.10 DLY3 (09h)
        11. 5.6.1.11 VGH (0Ah)
        12. 5.6.1.12 SS4 (0Bh)
        13. 5.6.1.13 FSW3 (0Ch)
        14. 5.6.1.14 DLY4 (0Dh)
        15. 5.6.1.15 OVP (0Eh)
        16. 5.6.1.16 FDIM (OFh)
        17. 5.6.1.17 RESET (10h)
        18. 5.6.1.18 VDET (11h)
        19. 5.6.1.19 DLY6 (12h)
        20. 5.6.1.20 VMAX (13h)
        21. 5.6.1.21 VMIN (14h)
        22. 5.6.1.22 USER (15h)
        23. 5.6.1.23 CONTROL (FFh)
      2. 5.6.2 VCOM Registers
        1. 5.6.2.1 VCOM DATA (Slave Address 28h, Register Address 00h)
        2. 5.6.2.2 VCOM CONTROL (Slave Address 28h, Register Address 02h)
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 External Component Selection
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 器件和文档支持
    1. 9.1 器件支持
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 接收文档更新通知
    3. 9.3 社区资源
    4. 9.4 商标
    5. 9.5 静电放电警告
    6. 9.6 Glossary
  10. 10机械、封装和可订购信息
    1. 10.1 封装信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Specifications

4.1 Absolute Maximum Ratings(1)

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
Pin voltage VIN, VCC, SCL, SDA, FLK, WP, XAO, COMP1 –0.3 7 V
AVDD, SW1, VCOM, NEG, BSUP, RST –0.3 12 V
EN, PWM –0.3 20 V
COMP2, COMP3, ISET –0.3 3.6 V
C1A, C1B –10 12 V
VGL –10 0.3 V
SW3, OVP –0.3 40 V
IFB1, IFB2, IFB3, IFB4, IFB5, IFB6, VGH, VGHM, RE, SW2 –0.3 30 V
Pin current SW2 TBD A
Ambient temperature, TA –40 85 °C
Junction temperature, TJ –40 150 °C
Storage temperature, TSTG –65 150 °C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

4.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) 2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) 700
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VIN Input voltage range Normal operation 2.0 5.5 V
EEPROM programming 2.6 5.5
dVIN/dt VIN rise time 0.45 11 ms
VBSUP Input voltage range 6.5 9.6 V
VBAT Input voltage range 4.5 24 V
dVBAT/dt VBAT rise time 0.45 11 ms
LINEAR REGULATOR (VCC)
VCC Output voltage 1.0 2.5 V
IICC Output current 300 mA
COUT Output capacitance 4.7 10 22 µF
BOOST CONVERTER 1 (AVDD)
AVDD Boost converter 1 output voltage range 6.5 9.6 V
IAVDD Boost converter 1 output current at VIN = 3.7 V 400 mA
L Inductance 4.7 10 15 µH
COUT Boost converter 1 output capacitance 4.7 10 22 µF
BOOST CONVERTER 2 (VGH)
AVDD Input voltage range 6.5 9.6 V
VGH Output voltage range 18 25.5 V
IGH Output current 25 mA
L Inductance 4.7 10 15 µH
COUT Output capacitance 1 4.7 10 µF
NEGATIVE CHARGE PUMP (VGL)
VGL Output voltage –5 –8 V
IGL Output current 25 mA
CFLY Flying capacitance 0.5 µF
COUT Output capacitance 0.5 5 µF
BOOST CONVERTER 3 (WLED)
VOUT Output voltage 38 V
IOUT Output current 250 mA
L Inductance 4.7 10 15 µH
COUT Output capacitance 2.2 4.7 10 µF
INTERNAL REGULATOR
COUT Capacitance connected to the TCOMP pin 1 µF

4.4 Thermal Information

THERMAL METRIC(1) TPS65154 UNIT
RSL (VQFN)
48 PIN
RθJA Junction-to-ambient thermal resistance 29.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.8 °C/W
RθJB Junction-to-board thermal resistance 5.2 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 5.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.8 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics application report.

4.5 Electrical Characteristics

VIN = 3.3 V, VLED = 12 V, VCC = 2.5 V, AVDD = 8 V, VGL = –6.8 V, VGH = 20 V, TA = −40°C to 85°C. Typical values are at 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
IIN Supply current into VIN pin Converters not switching 0.1 1 mA
IAVDD Supply current into AVDD pins Pins 2 and 3 connected together 0.75 2.5 mA
IBSUP Supply current into BSUP pin 2.5 5 mA
IGH Supply current into VGH pin No load on VGHM 0.1 1 mA
UNDERVOLTAGE LOCKOUT
VUVLO Undervoltage lockout threshold VIN falling 1.75 V
VIN rising 2.2
Hysteresis 90 mV
LINEAR REGULATOR (VCC)
VCC Linear regulator output voltage range 1.0 2.5 V
Tolerance ICC = 10 mA –3% +3%
VUVP Undervoltage protection threshold VCC falling 60% 70% 75%
VSCP Short circuit protection threshold VCC falling 25% 30% 40%
ILIM Current limit VCC = 5% below value at 10 mA. TJ = 25°C to 125°C 300 mA
TJ = –40°C 250
rDS(ON) Active pull-down resistance 10 21 35 Ω
BOOST CONVERTER 1 (AVDD)
AVDD Output voltage range 6.5 9.6 V
Tolerance –2% +2%
VUVP Undervoltage protection threshold 60% 70% 75%
VSCP Short-circuit protection threshold 25% 30% 35%
rDS(ON) Switch ON resistance ISW = 1 A 0.1 0.25 Ω
ILIM Switch current limit 2.4 3.0 3.6 A
rDS(ON) Rectifier ON resistance ISW = 1 A 0.25 0.4 Ω
fSW Switching frequency 400 1000 kHz
Tolerance –20% +20%
NEGATIVE CHARGE PUMP (VGL)
VGL Output voltage range –5 –8 V
Output voltage tolerance –3% 3.5%
VUVP Undervoltage protection threshold VGL rising 65% 70% 75%
VSCP Short-circuit protection threshold VGL rising 25% 30% 35%
IDRVN Maximum drive current C1B sinking 50 150 mA
C1B sourcing 60 160
VDO Dropout voltage fSW = 500 kHz, CFLY = 0.5 µF, IGL = 10 mA 0.6 1.0 V
fSW Switching frequency 400 500 600 kHz
rDS(ON) Discharge ON resistance IMEAS = 2 mA 2.1 3 3.9 kΩ
BOOST CONVERTER 2 (VGH)
VGH Output voltage range 18 25.5 V
Tolerance –3% 3%
VUVP Undervoltage protection threshold VGH falling 65% 70% 75%
VSCP Short-circuit protection threshold VGH falling 25% 30% 35%
rDS(ON) Switch ON resistance ISW = 1 A 0.3 1.0 Ω
tON(MAX) Maximum tON time 1 2 2.5 µs
tOFF tOFF time 2 2.7 4 µs
BOOST CONVERTER 3
VOUT Output voltage range VLED+2 38 V
ILIM Switch current limit 2.0 2.7 3.7 A
rDS(ON) Switch ON resistance ISW = 1 A 0.2 0.35 Ω
VOVP OVP range 30 39 V
Tolerance -5% +5%
VIL EN low input voltage EN falling 0.6 V
VIH EN high input voltage EN rising 1.5 V
VIH – VIL EN input hysteresis 0.09 0.16 0.27 V
RPULL-DOWN EN pull-down resistance 450 750 1250 kΩ
WLED DIMMING
IFB Maximum current 40 mA
Channel-to-channel current matching –3% +3%
Output dimming resolution 10 bits
DMIN Minimum output duty cycle 1%
DHYS Input PWM jitter hysteresis –0.048% 0.048%
VSET ISET regulation voltage –3% 1.0 +3% V
KSET ISET multiplication constant 1260 1296 1332
VIL PWM low input voltage PWM falling 0.6 V
VIH PWM high input voltage PWM rising 1.2 V
VIH – VIL PWM input voltage hysteresis 0.09 0.16 0.27 V
RPULL-DOWN PWM pull-down resistance 450 750 1250 kΩ
RESET (RST)
VOL Output voltage IRST = 1 mA (sinking) 0.2 0.5 V
IOH Leakage current VRST = 1.8 V 1 µA
PROGRAMMABLE VCOM
SETZSE VCOM DAC set zero-scale error VMIN = 07h, VMAX = 07h −7 7 LSB
VMAX DAC set zero-scale error –1 1
VMIN DAC set zero-scale error –1 1
SETFSE VCOM set full-scale error VMIN = 07h, VMAX = 07h −7 7 LSB
VMAX set full-scale error –1 1
VMIN set full-scale error −1 1
DNL Differential nonlinearity VCOM 1 LSB
VMAX 1
VMIN 1
BW Small-signal bandwidth Closed-loop; AV = –1; RF = 1 kΩ, RIN = 1 kΩ, VCM = 4 V; VSIGNAL = 63 mVpp; RL = ∞ 21 MHz
IOUT Peak output current Open-loop; VPOS = 4 V, VNEG = 3 V 400 mA
Open-loop; VPOS = 4 V, VNEG = –5 V 330
SR Slew rate Open-loop; VPOS = 4 V, VNEG = 5 V 36 V/µs
Open-loop; VPOS = 4 V, VNEG = 3 V 33
IIB– Input bias current (inverting input) Closed-loop; AV = +1; RF = 1 MΩ; VPOS = 4 V −1 1 μA
VDROP Output voltage drop Open-loop; VPOS = 4 V; IMEAS = 10 mA VNEG = 3 V 0.06 0.1 V
VNEG = 5 V 0.03 0.1
GATE VOLTAGE SHAPING
rDS(ON)H VGH to VGHM ON resistance VGH = 20 V, IGHM = 10 mA, VFLK = 1.8 V 13 25 Ω
rDS(ON)L VGHM to RE ON resistance VGHM = 20 V, IGHM = 10 mA, VFLK = 0 V 26 50 Ω
VGHM = 6 V, IGHM = 10 mA, VFLK = 0 V 26 50
VIL FLK low input voltage threshold VFLK falling 0.6 V
VIH FLK high input voltage threshold VFLK rising 1.2 V
VIH – VIL FLK input hysteresis 0.09 0.15 0.27 V
IIL FLK low input current VFLK = 0 V –100 100 nA
IIH FLK high input current VFLK = 1.8 V –100 100 nA
PANEL RESET (XAO)
VOL(XAO) Output voltage IXAO = 1 mA (sinking) 0.16 0.5 V
ILK(XAO) Leakage current VXAO = 1.8 V 1 µA
VDET XAO Threshold voltage range VIN falling VUVLO 3.0 V
Tolerance –3% +3%
Hysteresis VIN rising 0.05 0.3 V
I2C INTERFACE
ADDR Configuration parameters slave address 74h
Programmable VCOM slave address 28h
VIL Low level input voltage SCL or SDA falling, standard and fast modes 0.6 V
VIH High level input voltage SCL or SDA rising, standard and fast modes 1.0 V
VIH – VIL Input hysteresis 0.05 V
VOL Low level output voltage Sinking 3 mA 0.36 V
CI Input capacitance 10 pF
CB Capacitive load on SDA and SCL Standard mode 400 pF
Fast mode 400
EEPROM
VIL WP low input voltage threshold VWP falling 0.8 V
VIH WP high input voltage threshold VWP rising 1.2 V
VIH – VIL WP input voltage hysteresis 0.03 0.05 0.1 V
RPULL-UP WP internal pull-up resistor 20 60 100 kΩ
NWRITE Number of write cycles 1000
Data retention Storage temperature = 150 °C 100 1000 hrs
THERMAL SHUTDOWN
TSD Thermal shutdown temperature 150 °C
Thermal shutdown hysteresis 10

4.6 Timing Requirements

VIN = 3.3 V, VLED = 12 V, VCC = 2.5 V, AVDD = 8 V, VGL = –6.8 V, VGH = 20 V, TA = −40°C to 85°C. Typical values are at 25°C (unless otherwise noted).
MIN TYP MAX UNIT
LINEAR REGULATOR (VCC)
tDLY1 Linear regulator start-up delay time 0 75 ms
Tolerance –20% 30%
BOOST CONVERTER 1 (AVDD)
tSS2 Boost converter 1 soft-start duration range 0.5 75 ms
Tolerance –20% 30%
tDLY2 Boost converter 1 start-up delay range 0 75 ms
Tolerance –20% 30%
NEGATIVE CHARGE PUMP (VGL)
tSS3 Negative charge pump soft-start duration 0 35 ms
Tolerance –20% 30%
tDLY3 Negative charge pump start-up delay 0 35 ms
Tolerance –20% 30%
BOOST CONVERTER 2 (VGH)
tSS4 Boost converter 2 soft-start duration range 0 35 ms
Tolerance –20% 30%
BOOST CONVERTER 3
fSW Switching frequency range 400 1000 kHz
Tolerance –20% 20%
WLED DIMMING
tPWMIN Input pulse width 500 ns
fOUT Output frequency range Direct dimming 0.1 15 kHz
DPWM dimming 15 22
Tolerance –20% 20%
fIN Input frequency range PWM and direct dimming modes 0.1 15 kHz
RESET (RST)
tRST Reset pulse duration range 0 15 ms
Tolerance Measured from end of VCC's ramp to 50% of RST's rising edge with a 10 kΩ pull-up resistor. –20% 20%
GATE VOLTAGE SHAPING
tPLH Propagation delay VGHM rising, VFLK = 0 V/1.8 V, 50% thresholds, CVGHM = 150 pF, RE = 0 Ω 92 200 ns
tPHL VGHM falling, VFLK =0 V/1.8 V, 50% thresholds, CVGHM = 150 pF, RE = 0 Ω 88 200
tDLY4 Gate voltage shaping start-up delay range 0 35 ms
Tolerance –20% 30%
PANEL RESET (XAO)
tDLY6 Panel reset duration range 0 35 ms
Tolerance Measured from VIN = VDET to 50% of XAO's rising edge with a 10-kΩ pull-up resistor. –20% 30%
TIMING
tUVP Undervoltage protection timeout 40 50 60 ms
I2C INTERFACE
fSCL Clock frequency Standard mode 100 kHz
Fast mode 400
tLOW Clock low period Standard mode 4.7 µs
Fast mode 1.3
tHIGH Clock high period Standard mode 4.0 µs
Fast mode 0.6
tBUF Bus free time between a STOP and a START condition Standard mode 4.7 µs
Fast mode 1.3
thd:STA Hold time for a repeated START condition Standard mode 4.0 µs
Fast mode 0.6
tsu:STA Set-up time for a repeated START condition Standard mode 4.0 µs
Fast mode 0.6
tsu:DAT Data set-up time Standard mode 250 ns
Fast mode 100
thd:DAT Data hold time Standard mode 0.05 3.45 µs
Fast mode 0.05 0.9
tRCL1 Rise time of SCL after a repeated START condition and after an ACK bit Standard mode 20+0.1CB 1000 ns
Fast mode 20+0.1CB 1000
tRCL Rise time of SCL Standard mode 20+0.1CB 1000 ns
Fast mode 20+0.1CB 300
tFCL Fall time of SCL Standard mode 20+0.1CB 300 ns
Fast mode 20+0.1CB 300
tRDA Rise time of SDA Standard mode 20+0.1CB 1000 ns
Fast mode 20+0.1CB 300
tFDA Fall time of SDA Standard mode 20+0.1CB 300 ns
Fast mode 20+0.1CB 300
tsu:STO Set-up time for STOP condition Standard mode 4.0 µs
Fast mode 0.6
EEPROM
tWRITE Write time 100 ms
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