米6体育平台手机版

ZHCSF63A September 2013 – June 2016 TPS65154

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RSL|48
- MPQF193A

散热焊盘机械数据 (封装 | 引脚)

RSL|48
- QFND155N

订购信息

5 Detailed Description

5.1 Overview

The TPS65154 device integrates the bias and backlight functions needed by an active matrix liquid crystal display.

The LCD bias functions comprise

A synchronous boost converter to generate AV_DD
A non-synchronous boost converter to generate V_GH
An inverting charge pump to generate V_GL
An low dropout linear regulator to generate V_CC
A gate-voltage shaping function
A programmable VCOM buffer
XAO and RST signals
An I²C programming interface

The backlight driver functions comprise

A non-synchronous boost converter
A six-channel WLED driver with PWM dimming

The device configuration is stored in an on-chip nonvolatile memory, which can be programmed via an I²C interface.

5.2 Functional Block Diagram

Figure 5-1 shows a top-level block diagram of the TPS65154.

Figure 5-1 Top-Level Block Diagram

5.3 Feature Description

The following sections describe the features of the TPS65154.

5.3.1 Linear Regulator (V_CC)

The linear regulator is supplied directly from the VIN pin, and its output voltage can be programmed to 1.0 V, 1.2 V, 1.89 V, or 2.5 V using the VCC register.

Figure 5-2 Linear Regulator Block Diagram

5.3.1.1 Power-Up (Linear Regulator)

The linear regulator starts t_DLY1 milliseconds after the supply voltage exceeds the undervoltage lockout threshold (V_IN > V_UVLO). It does not have a soft-start function, and its output ramps up as fast as the supply voltage slew rate and the linear regulator's output capacitance allow.

5.3.1.2 Power-Down (Linear Regulator)

The linear regulator is turned off as soon as the supply voltage falls below the undervoltage lockout threshold (V_IN < V_UVLO). V_CC is actively discharged during power-down.

5.3.1.3 Protection (Linear Regulator)

The linear regulator is protected against short-circuits and undervoltage conditions. An undervoltage condition is detected if the linear regulator's output falls below 70% of its programmed voltage for longer than 50 ms, in which case the IC is disabled. A short-circuit condition is detected if the linear regulator's output falls below 30% of its programmed voltage, in which case the IC is disabled immediately (short-circuit detection has no time delay associated with it). To recover normal operation following either an undervoltage condition or short-circuit condition, the cause of the error must be removed and a POR applied.

5.3.2 Boost Converter 1 (AV_DD)

Boost converter 1 is synchronous and uses a virtual current mode topology that:

achieves high efficiencies;
allows the converter to work in continuous conduction mode under all operating conditions, simplifying compensation; and
provides true input-output isolation when the boost converter is disabled.

Figure 5-3 Boost Converter 1 Internal Block Diagram

Boost converter 1's switching frequency can be programmed to 400 kHz, 600 kHz, 800 kHz, or 1 MHz using the FSW1 register. Its output voltage can be programmed from 6.5 V to 9.6 V in 100 mV steps using the AVDD register.

Boost converter 1 uses an external compensation network connected to the COMP1 pin to stabilize its feedback loop. A simple series R-C network connected between the COMP1 pin and ground is sufficient to achieve good performance, that is, stable and with good transient response. Good starting values, which will work for most applications, are 25 kΩ and 3.9 nF.

In some applications (for example, those using electrolytic output capacitors), it may be necessary to include a second compensation capacitor between the COMP1 pin and ground. This has the effect of adding an additional pole in the feedback loop's frequency response, which cancels the zero introduced by the output capacitor's ESR.

The synchronous topology of boost converter 1 ensures that AV_DD is fully isolated from V_IN when the converter is disabled.

5.3.2.1 Power-Up (Boost Converter 1)

Boost converter 1 starts t_DLY2 milliseconds after RST goes high. Delay time t_DLY2 can be programmed from 0 ms to 75 ms using the DLY2 register.

To minimize inrush current during start-up, boost converter 1 ramps its output voltage in t_SS2 milliseconds. Start-up time t_SS2 can be programmed from 0.5 ms to 75 ms using the SS2 register. Longer soft-start times generate lower inrush currents.

5.3.2.2 Power-Down (Boost Converter 1)

Boost converter 1 is disabled when V_IN<V_UVLO. When disabled, boost converter 2 actively discharges AV_DD by turning on Q2.

5.3.2.3 Protection (Boost Converter 1)

Boost converter 1 is protected against short-circuits and undervoltage conditions. An undervoltage condition is detected if the boost converter's output falls below 70% of its programmed voltage for longer than 50 ms, in which case the IC is disabled. A short-circuit condition is detected if the boost converter's output falls below 30% of its programmed voltage, in which case the IC is disabled immediately (short-circuit detection has no time delay associated with it). To recover normal operation following either an undervoltage condition or short-circuit condition, the cause of the error must be removed and a POR applied.

5.3.3 Boost Converter 2 (V_GH)

Boost converter 2 is non-synchronous and uses a constant off-time topology. The converter's switching frequency is not constant but adapts itself to V_IN and V_GH. Boost converter 2 uses peak current control and is designed to operate permanently in discontinuous conduction mode (DCM), thereby allowing the internal compensation circuit to achieve stable operation over a wide range of output voltages and currents. Boost converter 2's output voltage can be programmed from 18 V to 25.5 V using the VGH register.

Figure 5-4 Boost Converter 2 Block Diagram

5.3.3.1 Power-Up (Boost Converter 2)

Boost converter 2 is enabled as soon as V_GL has finished ramping down. To minimize inrush current during start-up, boost converter 2 ramps V_GH linearly to its programmed value in t_SS4 seconds. Soft-start time t_SS4 can be programmed from 0.256 ms to 35 ms using the SS4 register. Because boost converter 2 is non-synchronous, its output is already equal to AV_DD (minus the voltage drop across its rectifier diode) before it starts switching, which means that the time during which V_GH is actually ramping during start-up is less than the actual programmed soft-start time (see Figure 5-5).

Figure 5-5 Boost Converter 2 Soft-Start

5.3.3.2 Power-Down (Boost Converter 2)

Boost converter 2 is disabled when V_IN<V_UVLO. The converter's output is not actively discharged when the converter is disabled.

5.3.3.3 Protection (Boost Converter 2)

Boost converter 2 is protected against short-circuits and undervoltage conditions. An undervoltage condition is detected if the boost converter's output falls below 70% of its programmed voltage for longer than 50 ms, in which case the IC is disabled. A short-circuit condition is detected if the boost converter's output falls below 30% of its programmed voltage, in which case the IC is disabled immediately (short-circuit detection has no time delay associated with it). To recover normal operation following either an undervoltage condition or short-circuit condition, the cause of the error must be removed and a POR applied.

5.3.4 Negative Charge Pump (V_GL)

The negative charge pump inverts AV_DD and regulates its output to the voltage set by the VGL register. V_GL can be programmed from –5 V to –8 V in 0.2 V steps using the VGL register, however, since the negative charge pump inverts AV_DD to generate its output, the most negative voltage that can be generated is approximately –AV_DD+1 V. Thus, if AV_DD= 8.0 V, the usable range of V_GL is approximately –5 V to –7 V. If V_GL is programmed to a more negative voltage than this the charge pump may not be able to regulate its output. This will not damage the IC, but performance may be impaired.

The negative charge pump in the TPS65154 is fully integrated and requires only two external capacitors to operate (a flying capacitor connected between the C1A and C1B pins, and an output capacitor connected between the VGL pin and ground).

Figure 5-6 Negative Charge Pump Block Diagram

5.3.4.1 Power-Up (Negative Charge Pump)

The negative charge pump starts t_DLY3 milliseconds after boost converter 1 (AV_DD) starts ramping and ramps its output linearly from zero to its programmed output voltage in t_SS3 ms. Delay time t_DLY3 can be programmed from 0 ms to 35 ms using the DLY3 register. Soft-start time t_SS3 can be programmed from 0 ms to 35 ms using the SS3 register.

5.3.4.2 Power-Down (Negative Charge Pump)

The negative charge pump is disabled when the supply voltage falls below the undervoltage lockout threshold (V_IN<V_UVLO). During power-down the charge pump's output is actively discharge to GND.

5.3.4.3 Protection (Negative Charge Pump)

The negative charge pump is protected against short-circuits and undervoltage conditions. An undervoltage condition is detected if the charge pump's output falls below 70% of its programmed voltage for longer than 50 ms, in which case the IC is disabled. A short-circuit condition is detected if the charge pump's output falls below 30% of its programmed voltage, in which case the IC is disabled immediately (short-circuit detection has no time delay associated with it). To recover normal operation following either an undervoltage condition or short-circuit condition, the cause of the error must be removed and a POR applied.

5.3.5 Gate Voltage Shaping

The gate voltage shaping function can be used to reduce image sticking in LCD panels by modulating the LCD panel's gate ON voltage (V_GH). Figure 5-7 shows a block diagram of the gate voltage shaping function and Figure 5-8 shows the typical waveforms during operation.

Figure 5-7 Gate Voltage Shaping Block Diagram

Figure 5-8 Gate Voltage Shaping Waveforms

Gate voltage shaping is controlled by the FLK input. When FLK is high, Q1 is on, Q2, Q3 and Q4 are off, and V_GHM is equal to V_GH. On the falling edge of FLK, Q1 is turned off, Q2 and Q3 are turned on, and the LCD panel load connected to the VGHM pin discharges through the external resistor connected to the RE pin.

During power-up, Q1, Q2 and Q3 are held off and Q4 is turned on, pulling the VGHM pin pulled to GND, regardless of the state of the FLK signal, until t_DLY4 milliseconds after boost converter 2 (V_GH) has finished ramping. The value of t_DLY4 can be programmed from 0 ms to 35 ms using the DLY4 register.

During power-down Q1 is held permanently on and Q2, Q3 and Q4 permanently off, regardless of the state of the FLK signal.

5.3.6 Panel Discharge (XAO)

The TPS65154 provides an output signal via its XAO pin that can be used to drive the outputs of the display panel's gate driver IC high during power-down. The XAO pin is pulled low whenever V_IN<V_DET. The V_DET threshold voltage can be configured using the VDET register.

The XAO output is an open-drain type and requires an external pull-up, typically in the range 10 kΩ to 100 kΩ.

5.3.7 Reset Generator (RST)

The RST pin generates an active-low reset signal for the rest of the system. During power-up, the reset timer starts when V_CC has finished ramping. The reset pulse duration t_RST can be programmed from 0 ms to 15 ms using the RESET register. The RST signal is latched when it goes high and will not be taken low again until the device is powered down (even if V_CC temporarily falls out of regulation). The active power-down threshold (V_UVLO or V_DET) can be selected using the RMODE bit in the CONFIG register.

The RST output is an open-drain type that requires an external pull-up resistor. Pull-up resistor values in the range 10 kΩ to 100 kΩ are recommended for most applications.

5.3.8 Programmable VCOM

The programmable VCOM uses three digital-to-analog converters (DACs) to generate a V_COM voltage that is subsequently buffered by a high-speed op-amp. The maximum value of V_COM is set by the 4-bit VMAX register, and can be programmed in the range 2.5/8×AV_DD to 4/8×AV_DD. The minimum value of V_COM is set by the 4-bit VMIN register, and can be programmed in the range 2/8 × AV_DD to 3.5/8 × AV_DD. Note, for proper operation, V_MAX must be greater than V_MIN. By programming the 7-bit VCOM parameter, users can adjust the V_COM voltage appearing at the OUT pin between V_MIN and V_MAX as follows:

Equation 1. TPS65154 VCOM_equation.gif

where VCOM is the value stored in the Wiper Register (see Figure 5-9).

Figure 5-9 Programmable VCOM Block Diagram

The programmable VCOM function has three registers. The volatile Wiper Register (WR) contains the value currently output by the programmable VCOM DAC; this value is lost when power to the device is removed. The non-volatile Initial Value Register (IVR) contains the value loaded into the DAC every time the device is powered up. The Control Register (CR) determines whether data is written to or read from the WR, the IVR, or both. If the CR contains 00h, during write operations data is stored in the WR and the IVR, and during read operations data is read from the IVR. If the CR contains 80h, data is written to and read from the WR register only. 00h and 80h are the only valid values for the CR. Table 5-1 shows the programmable VCOM's register address map.

Table 5-1 Programmable VCOM Register Address Map

REGISTER ADDRESS	NON-VOLATILE	VOLATILE
00h	Initial Value Register (IVR)	Wiper Register (WR)
02h	Not Used	Control Register (CR)

5.3.8.1 Operational Amplifier Performance

Like most op-amps, the V_COM op-amp in the TPS65154 is not designed to drive purely capacitive loads, so it is not recommended to connect a capacitor directly to its output in an attempt to increase performance; however, the op-amp is capable of delivering high peak currents that make such capacitors unnecessary in most applications.

High-speed op amps such as the one in the TPS65154 require care when using them. The most common problem is when parasitic capacitance at the inverting input creates a pole with the feedback resistor, reducing amplifier stability. Two things can be done to minimize the likelihood of this happening. Both of these work by shifting the pole (which can never be completely eliminated) to a frequency outside the op amp's bandwidth, where it has no effect.

Reduce the value of the feedback resistor. In applications where no feedback from the panel is used, the feedback resistor can be made zero. In applications where a non-zero feedback resistor has to be used, a small capacitor (between 10 pF and 100 pF) across the feedback resistor will minimize ringing.
Minimize the parasitic capacitance at the op amp's inverting input. This is achieved by using short PCB traces between the feedback resistor and the inverting input, and by removing ground planes and other copper areas above and below this PCB trace.

5.3.8.2 Power-Up (Programmable VCOM)

The programmable V_COM is enabled when AV_DD > V_UVLO2.

5.3.8.3 Power-Down (Programmable VCOM)

During power-down, the programmable VCOM continues to operate until AV_DD < V_UVLO2.

5.3.9 WLED Driver

5.3.9.1 WLED Boost Converter

The WLED boost converter boosts a 4.5 V to 24 V supply V_BAT to a higher voltage to supply the LED strings connected to the WLED driver. It uses a fixed-frequency, current-mode topology. The converter's output voltage is automatically adjusted to maintain the lowest feedback voltage (IFB1 to IFB6) between 450 mV and 750 mV, thus ensuring sufficient headroom for the output current sinks, but without dissipating excessive power in the IC. This approach automatically compensates for changes in the LED string voltage, for example, because of temperature effects. The WLED boost converter's switching frequency can be programmed to 400 kHz, 600 kHz, 800 kHz, and 1 MHz using the FSW3 register.

The WLED boost converter features a soft-start circuit to limit inrush current when the converter starts. The duration of the soft-start ramp depends on the value of the capacitor connected to the COMP3 pin. Note, that because the converter is a non-synchronous type, its output voltage before it starts switching is equal to V_BAT (minus the voltage drop across its rectifier).

5.3.9.2 Current Sinks

The brightness of the LED strings is determined by the average current flowing through each string, which is the product of the output duty cycle and the current sink's output current. The output current of all current sinks is the same and is set by the external resistor connected between the ISET pin and ground:

Equation 2. TPS65154 wled_iset_equation_lvsbg2.gif

where:

V_SET is the voltage on the ISET pin
R_SET is the resistance between the ISET pin and GND
K_SET is a constant

When the TPS65154 measures zero current flowing in one of the IFB pins it determines that the string is open and automatically disables that output. The WLED boost converter's output voltage is subsequently regulated according to the remaining operational strings. If an application uses fewer than six LED strings, it is recommended to connected the unused outputs to ground; this ensures the most rapid detection of the unused strings. Once open strings have been detected, they remain disabled until a POR occurs or EN is toggled.

5.3.9.3 Protection

The WLED boost converter and dimming circuits feature a variety of protection schemes to ensure reliable operation when subjected to various failure modes. These protection schemes are listed in Table 5-2.

Table 5-2 WLED Driver Protection

ERROR	DETECTION	ACTION	RECOVERY
WLED boost converter output voltage too high	V_OVP exceeds programmed threshold (30 V, 33 V, 36 V or 39 V)	WLED boost converter output regulated to programmed threshold	None required
WLED boost converter switch current too high	I_SW > I_LIM	Switch turned off	Switch automatically re-enabled at start of next switching cycle
All LED strings open-circuit	I_IFB = 0 mA and V_OUT = V_OVP	Disable all output channels and boost converter	Output channels re-enabled following power cycle
Individual LED string(s) open-circuit	I_IFB = 0 mA and V_OUT = V_OVP	Disable affected output channel(s) Functional output channels continue operating.	Affected output channel(s) re-enabled following power cycle
Individual LED string(s) shorted-circuited to ground	I_IFB = 0 mA for longer than 4 ms		Affected output channel(s) re-enabled following power cycle

5.3.9.4 Enable and Start-Up

The WLED driver is enabled and disabled by EN, however, this signal has no effect until the LCD bias functions have completed their start-up sequence. Following a POR, EN has no effect until t_DLY4 is complete; after that the WLED driver can be enabled and disabled at any time using EN (providing nothing happens to cause the LCD bias functions to re-start) and applying a PWM signal. In applications that do not generate an EN signal, the EN pin can be tied to V_IN, in which case the WLED driver will start automatically at the end of t_DLY4. Note, that a permanently low PWM signal (0% duty cycle) will prevent boost converter 3 from starting-up.

When the WLED driver is enabled it first checks the status of IFB1 to IFB6 and shuts down any channels that it detects are disabled/unused. These channels will be subsequently ignored until a POR occurs or EN is toggled.

5.3.10 Undervoltage Lockout

An undervoltage lockout function disables the IC when the supply voltage is too low for proper operation.

5.4 Device Functional Modes

5.4.1 Dimming Modes

The TPS65154 support direct dimming and phase-shift dimming modes. The active dimming mode can be selected using the DMODE bit in the CONFIG register.

5.4.1.1 Direct Dimming

When direct dimming is selected, the output current sinks are controlled directly by the PWM signal. In this mode, they are turned on and off together, at the same frequency and duty cycle as the PWM signal (see Figure 5-10).

Figure 5-10 Direct Dimming

5.4.1.2 Phase-Shift Dimming

When phase-shift dimming mode is selected, the output dimming frequency does not depend on the frequency of the PWM signal but can be independently programmed from 15 kHz to 22 kHz using the FDIM register. In this mode, the duty cycle information contained in the PWM signal is extracted and re-used to generate up to six outputs, at the output frequency set by the FDIM register, and phase-shifted with respect to each other by 360°/N, where N is the number of outputs in use (see Figure 5-11). Using phase-shifted outputs, the maximum load current step is reduced by the same factor N, resulting in reduced voltage ripple on the boost converter's output and consequently lower audible noise.

Figure 5-11 Phase-Shift Dimming

5.4.2 Power Sequencing

Figure 5-12 shows the typical power-up/down characteristic of the TPS65154.

5.4.2.1 Power-Up

V_CC starts ramping t_DLY1 seconds after V_IN > V_UVLO.

RST is initially held low. t_RST seconds after V_CC has finished ramping RST goes high.

AV_DD starts ramping t_DLY2 seconds after RST has gone high.

V_GL starts ramping t_DLY3 seconds after AV_DD starts ramping.

V_GH starts ramping as soon as V_GL has finished ramping.

V_GHM is initially held low (connected to RE). t_DLY4 seconds after V_GH has finished ramping, gate voltage shaping is enabled and V_GHM follows the state of FLK.

XAO is initially held low. t_DLY6 seconds after V_IN>V_DET XAO goes high.

The WLED driver is enabled by the logical AND of AV_DD (that is, AV_DD has finished ramping) and EN.

5.4.2.2 Power-Down

V_CC, AV_DD, V_GH and V_GL are disabled when V_IN<V_UVLO.

XAO goes low when V_IN falls below the threshold selected for it (V_UVLO or V_DET).

RST goes low when V_IN falls below the threshold selected for it (V_UVLO or V_DET).

The WLED driver is turned off when EN = 0 or V_IN < V_UVLO.

Figure 5-12 Power Up/Down Sequencing

5.5 Programming

5.5.1 Configuration

The TPS65154 divides the configuration parameters into two categories:

Configuration parameters
VCOM

In typical applications, all configuration parameters except VCOM are programmed by the subcontractor during PCB assembly, and VCOM is programmed by the display manufacturer during display calibration.

5.5.1.1 General

Configuration parameters can be changed by writing the desired values to the appropriate RAM register(s). The RAM registers are volatile and their contents are lost when power is removed from the device. By writing to the Control Register, it is possible to store the active configuration in non-volatile EEPROM; during power-up, the contents of the EEPROM are copied into the RAM registers and used to configure the device.

5.5.1.1.1 I²C Interface

The TPS65154 features an industry-standard I²C interface that supports both Standard and Fast modes of operation.

5.5.1.1.2 Slave Addresses

The configuration parameters are all accessed using slave address 74h and the VCOM is accessed using slave address 28h.

5.5.1.1.3 Write Protect

An active-high Write Protect pin (WP) prevents the configuration parameters from being changed by accident. This pin is internally pulled high and must be actively pulled low to access to the EEPROM or RAM registers. Note that the WP pin disables all I²C traffic to the TPS65154, and must also be pulled low during read operations. This is to ensure that noise present on the I²C lines does not erroneously overwrite the active configuration stored in RAM (which would not be protected by a simple EEPROM write-protect scheme). The write protect function can be enabled and disabled using the WPEN bit in the CONFIG register. Note that once the write protect function is enabled it is not possible to disable again it without pulling the WP pin low. For this reason, it is strongly recommended that applications include some way to pull the WP pin low (for example, a test pad), even if it is not normally used.

5.5.2 Programming Examples (Excluding VCOM)

5.5.2.1 Writing to a Single RAM Register

Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h)
TPS65154 acknowledges
Bus master sends address of RAM register (00h)
TPS65154 acknowledges
Bus master sends data to be written
TPS65154 acknowledges
Bus master sends STOP condition

Figure 5-13 Writing to a Single RAM Register

5.5.2.2 Writing to Multiple RAM Registers

Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h).
TPS65154 acknowledges
Bus master sends address of first RAM register to be written to (00h)
TPS65154 acknowledges
Bus master sends data to be written to first RAM register
TPS65154 acknowledges
Bus master sends data to be written to RAM register at next higher address (auto-increment)
TPS65154 acknowledges
Steps (8) and (9) repeated until data for final RAM register has been sent
TPS65154 acknowledges
Bus master sends STOP condition

Figure 5-14 Writing to Multiple RAM Registers

5.5.2.3 Saving Contents of all RAM Registers to EEPROM

Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h)
TPS65154 acknowledges
Bus master sends address of Control Register (FFh)
TPS65154 acknowledges
Bus master sends data to be written to the Control Register (80h)
TPS65154 acknowledges
Bus master sends STOP condition

Figure 5-15 Saving Contents of all RAM Registers to EEPROM

5.5.2.4 Reading from a Single RAM Register

Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h)
TPS65154 acknowledges
Bus master sends address of Control Register (FFh)
TPS65154 acknowledges
Bus master sends data for Control Register (00h)
TPS65154 acknowledges
Bus master sends STOP condition
Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h)
TPS65154 acknowledges
Bus master sends address of RAM register (00h)
TPS65154 acknowledges
Bus master sends REPEATED START condition
Bus master sends 7-bit slave address plus high R/W bit (E9h)
TPS65154 acknowledges
TPS65154 sends RAM register data
Bus master does not acknowledge
Bus master sends STOP condition

Figure 5-16 Reading from a Single RAM Register

5.5.2.5 Reading from a Single EEPROM Register

Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h)
TPS65154 acknowledges
Bus master sends address of Control Register (FFh)
TPS65154 acknowledges
Bus master sends data for Control Register (01h)
TPS65154 acknowledges
Bus master sends STOP condition
Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h)
TPS65154 acknowledges
Bus master sends address of EEPROM register (00h)
TPS65154 acknowledges
Bus master sends REPEATED START condition
Bus master sends 7-bit slave address plus high R/W bit (E9h)
TPS65154 acknowledges
TPS65154 sends EEPROM register data
Bus master does not acknowledge
Bus master sends STOP condition

Figure 5-17 Reading from a Single EEPROM Register

5.5.2.6 Reading from Multiple RAM Registers

Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h)
TPS65154 acknowledges
Bus master sends address of Control Register (FFh)
TPS65154 acknowledges
Bus master sends data for Control Register (00h)
TPS65154 acknowledges
Bus master sends STOP condition
Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h)
TPS65154 acknowledges
Bus master sends address of first register to be read (00h)
TPS65154 acknowledges
Bus master sends REPEATED START condition
Bus master sends 7-bit slave address plus high R/W bit (E9h)
TPS65154 acknowledges
TPS65154 sends contents of first RAM register to be read
Bus master acknowledges
TPS65154 sends contents of second RAM register to be read
Bus master acknowledges
TPS65154 sends contents of third (last) RAM register to be read
Bus master does not acknowledge
Bus master sends STOP condition

Figure 5-18 Reading from Multiple RAM Registers

5.5.2.7 Reading from Multiple EEPROM Registers

Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h)
TPS65154 acknowledges
Bus master sends address of Control Register (FFh)
TPS65154 acknowledges
Bus master sends data for Control Register (01h)
TPS65154 acknowledges
Bus master sends STOP condition
Bus master sends START condition
Bus master sends 7-bit slave address plus low R/W bit (E8h)
TPS65154 acknowledges
Bus master sends address of first EEPROM register to be read (00h)
TPS65154 acknowledges
Bus master sends REPEATED START condition
Bus master sends 7-bit slave address plus high R/W bit (E9h)
TPS65154 acknowledges
TPS65154 sends contents of first EEPROM register to be read
Bus master acknowledges
TPS65154 sends contents of second EEPROM register to be read
Bus master acknowledges
TPS65154 sends contents of third (last) EEPROM register to be read
Bus master does not acknowledge
Bus master sends STOP condition

Figure 5-19 Reading from Multiple EEPROM Registers

5.5.3 Programming Examples - VCOM

5.5.3.1 Writing a VCOM Value of 77h to WR

The bus master sends a START condition.
The bus master sends 7-bit slave address plus low R/W bit.
TPS65154 slave acknowledges.
The bus master sends the CR address of 02h.
The TPS65154 acknowledges.
The bus master sends the CR contents of 80h.
The TPS65154 slave acknowledges.
The bus master sends a STOP condition.
The bus master sends a START condition.
The bus master sends 7-bit slave address plus low R/W bit.
TPS65154 slave acknowledges.
The bus master sends the WR address of 00h.
The TPS65154 acknowledges.
The bus master sends the WR contents of 77h (right-justified).
The TPS65154 slave acknowledges.
The bus master sends a STOP condition.

Figure 5-20 Writing a VCOM Value of 77h to WR

5.5.3.2 Writing a VCOM Value of 77h to IVR and WR

The bus master sends a START condition.
The bus master sends 7-bit slave address plus low R/W bit.
TPS65154 slave acknowledges.
The bus master sends the CR address of 02h.
The TPS65154 acknowledges.
The bus master sends the CR contents of 00h.
The TPS65154 slave acknowledges.
The bus master sends a STOP condition.
The bus master sends a START condition.
The bus master sends 7-bit slave address plus low R/W bit.
TPS65154 slave acknowledges.
The bus master sends the WR address of 00h.
The TPS65154 acknowledges.
The bus master sends the WR contents of 77h (right-justified).
The TPS65154 slave acknowledges.
The bus master sends a STOP condition.

Figure 5-21 Writing a VCOM Value of 77h to IVR and WR

5.5.3.3 Reading a VCOM Value of 77h from WR

The bus master sends a START condition.
The bus master sends 7-bit slave address plus low R/W bit.
TPS65154 slave acknowledges.
The bus master sends the CR address of 02h.
The TPS65154 acknowledges.
The bus master sends the CR contents of 80h.
The TPS65154 slave acknowledges.
The bus master sends a STOP condition.
The bus master sends a START condition.
The bus master sends 7-bit slave address plus low R/W bit.
TPS65154 slave acknowledges.
The bus master sends the WR address of 00h.
The TPS65154 acknowledges.
The bus master sends a REPEATED START condition.
The bus master sends 7-bit slave address plus high R/W bit.
The TPS65154 sends the WR contents of 77h (right-justified).
The bus master does not acknowledge.
The bus master sends a STOP condition.

Figure 5-22 Reading 77h from WR

5.5.3.4 Reading a VCOM Value of 77h from IVR

The bus master sends a START condition.
The bus master sends 7-bit slave address plus low R/W bit.
TPS65154 slave acknowledges.
The bus master sends the CR address of 02h.
The TPS65154 acknowledges.
The bus master sends the CR contents of 00h.
The TPS65154 slave acknowledges.
The bus master sends a STOP condition.
The bus master sends a START condition.
The bus master sends 7-bit slave address plus low R/W bit.
TPS65154 slave acknowledges.
The bus master sends the WR address of 00h.
The TPS65154 acknowledges.
The bus master sends a REPEATED START condition.
The bus master sends 7-bit slave address plus high R/W bit.
The TPS65154 sends the WR contents of 77h (right-justified).
The bus master does not acknowledge.
The bus master sends a STOP condition.

Figure 5-23 Reading 77h from IVR

5.6 Register Map

5.6.1 Configuration Registers (Excluding VCOM)

Table 5-3 shows the memory map of the configuration parameters.

Table 5-3 Configuration Memory Map

REGISTER ADDRESS	REGISTER NAME	FACTORY DEFAULT		DESCRIPTION
00h	CONFIG	02h	KMODE = 0 WPEN = 0 DMODE = 1 RMODE = 0	Sets miscellaneous configuration bits
01h	VCC	03h	2.5 V	Sets the output voltage of the linear regulator (V_CC)
02h	DLY1	02h	10 ms	Sets the start-up delay of the linear regulator (V_CC)
03h	AVDD	0Fh	8.0 V	Sets the output voltage of boost converter 1 (AV_DD)
04h	FSW1	01h	600 kHz	Sets the switching frequency of boost converter 1 (AV_DD)
05h	SS2	04h	20 ms	Sets the soft-start time of boost converter 1 (AV_DD)
06h	DLY2	02h	10 ms	Sets the start-up delay of boost converter 1 (AV_DD)
07h	VGL	09h	–6.8 V	Sets the output voltage of the negative charge pump (V_GL)
08h	SS3	01h	5 ms	Sets the soft-start time of the negative charge pump (V_GL)
09h	DLY3	01h	5 ms	Sets the start-up delay of the negative charge pump (V_GL)
0Ah	VGH	04h	20.0 V	Sets the output voltage of boost converter 2 (V_GH)
0Bh	SS4	01h	5 ms	Sets the soft-start time of boost converter 2 (V_GH)
0Ch	FSW3	01h	600 kHz	Sets the switching frequency of boost converter 3 (WLED)
0Dh	DLY4	02h	10 ms	Sets the start-up delay of the gate voltage shaping function (V_GHM)
0Eh	OVP	03h	39 V	Sets the over-voltage protection threshold of boost converter 3 (WLED)
0Fh	FDIM	07h	22 kHz	Sets the output dimming frequency of the WLED driver in phase-shift dimming mode
10h	RESET	05h	5 ms	Sets the reset pulse duration
11h	VDET	00h	V_DET = V_UVLO	Sets the threshold of the RST and XAO signals
12h	DLY6	02h	30 ms	Sets the start-up delay of the XAO signal
13h	VMAX	07h	3.2 V	Sets the maximum V_COM voltage
14h	VMIN	07h	2.7 V	Sets the minimum V_COM voltage
15h	USER1	00h	00h	For customer use
FFh	CONTROL	00h		Controls whether read and write operations access RAM or EEPROM registers

5.6.1.1 CONFIG (00h)

The CONFIG register can be written to and read from.

Figure 5-24 CONFIG Register Bit Allocation

7	6	5	4	3	2	1	0
ADIS	Reserved			KMODE	WPEN	DMODE	RMODE
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-1	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-4 CONFIG Register Field Descriptions

Bit	Field	Value	Description
7	ADIS		This bit can be used to disable boost converter 1 (AV_DD), boost converter 2 (V_GH) and the negative charge pump (V_GL) during device programming. This bit is volatile and is never stored in EEPROM. It is always reset (that is, ADIS = 0) following power-up, that is, the affected converters are always enabled following power-up.
		0	Boost converter 1 (AV_DD), boost converter 2 (V_GH), and negative charge pump (V_GL) enabled.
		1	Boost converter 1 (AV_DD), boost converter 2 (V_GH), and negative charge pump (V_GL) disabled.
6-4	Reserved	N/A	These bits are reserved for future use and should be programmed to 0 to ensure proper operation.
3	KMODE		This bit can be used to enable and disable boost converter 1's active discharge function.
		0	Boost converter 1 (AV_DD) active discharge enabled.
		1	Boost converter 1 (AV_DD) active discharge disabled.
2	WPEN		This bit can be used to enable and disable the write protect function.
		0	Disabled. WP not used and I²C interface always active.
		1	Enabled. I²C interface only active when WP pulled low.
1	DMODE		This bit determines which dimming mode is used by the WLED driver.
		0	Direct dimming.
		1	Phase-shift dimming.
0	RMODE		This bit determines which threshold is used to assert RST during power-down.
		0	V_UVLO threshold used.
		1	V_DET threshold used.

5.6.1.2 VCC (01h)

The VCC register can be written to and read from.

Figure 5-25 VCC Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented						VCC
						R/W-1	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-5 VCC Register Field Descriptions

Bit	Field	Value	Description
7-2	Not implemented	N/A	These bits are not implemented. During write operations, data for these bits is ignored, and during read operations 0 is returned.
1-0	VCC		These bits determine the output voltage of the linear regulator (V_CC).
		0h	1.0 V
		1h	1.2 V
		2h	1.89 V
		3h	2.5 V

5.6.1.3 DLY1 (02h)

The DLY1 register can be written to and read from.

Figure 5-26 DLY1 Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented				DLY1
				R/W-0	R/W-0	R/W-1	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-6 DLY1 Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during write operations 0 is returned.
3-0	DLY1		These bits determine how soon after V_IN>V_UVLO the linear regulator (V_CC) starts.
		0h	0 ms
		1h	5 ms
		2h	10 ms
		3h	15 ms
		4h	20 ms
		5h	25 ms
		6h	30 ms
		7h	35 ms
		8h	40 ms
		9h	45 ms
		Ah	50 ms
		Bh	55 ms
		Ch	60 ms
		Dh	65 ms
		Eh	70 ms
		Fh	75 ms

5.6.1.4 AVDD (03h)

The AVDD register can be written to and read from.

Figure 5-27 AVDD Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented			AVDD
			R/W-0	R/W-1	R/W-1	R/W-1	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-7 AVDD Register Field Descriptions

Bit	Field	Value	Description
1	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
0	AVDD		These bits determine the output voltage of boost converter 1 (AV_DD).
		00h	6.5 V
		01h	6.6 V
		02h	6.7 V
		03h	6.8 V
		04h	6.9 V
		05h	7.0 V
		06h	7.1 V
		07h	7.2 V
		08h	7.3 V
		09h	7.4 V
		0Ah	7.5 V
		0Bh	7.6 V
		0Ch	7.7 V
		0Dh	7.8 V
		0Eh	7.9 V
		0Fh	8.0 V
		10h	8.1 V
		11h	8.2 V
		12h	8.3 V
		13h	8.4 V
		14h	8.5 V
		15h	8.6 V
		16h	8.7 V
		17h	8.8 V
		18h	8.9 V
		19h	9.0 V
		1Ah	9.1 V
		1Bh	9.2 V
		1Ch	9.3 V
		1Dh	9.4 V
		1Eh	9.5 V
		1Fh	9.6 V

5.6.1.5 FSW1 (04h)

The FSW1 register can be written to and read from.

Figure 5-28 FSW1 Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented						FSW1
						R/W-0	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-8 FSW1 Register Field Descriptions

Bit	Field	Value	Description
7-2	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
1-0	FSW1		These bits determine the switching frequency of boost converter 1 (AV_DD).
		0h	400 kHz
		1h	600 kHz
		2h	800 kHz
		3h	1 MHz

5.6.1.6 SS2 (05h)

The SS2 register can be written to and read from.

Figure 5-29 SS2 Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented				SS2
				R/W-0	R/W-1	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-9 SS2 Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	SS2		These bits determine the soft-start time of boost converter 1 (AV_DD).
		0h	0.5 ms
		1h	5 ms
		2h	10 ms
		3h	15 ms
		4h	20 ms
		5h	25 ms
		6h	30 ms
		7h	35 ms
		8h	40 ms
		9h	45 ms
		Ah	50 ms
		Bh	55 ms
		Ch	60 ms
		Dh	65 ms
		Eh	70 ms
		Fh	75 ms

5.6.1.7 DLY2 (06h)

The DLY2 register can be written to and read from.

Figure 5-30 DLY2 Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented				DLY2
				R/W-0	R/W-0	R/W-1	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-10 DLY2 Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	DLY2		These bits determine how soon after RST goes high boost converter 1 (AV_DD) starts.
		0h	0 ms
		1h	5 ms
		2h	10 ms
		3h	15 ms
		4h	20 ms
		5h	25 ms
		6h	30 ms
		7h	35 ms
		8h	40 ms
		9h	45 ms
		Ah	50 ms
		Bh	55 ms
		Ch	60 ms
		Dh	65 ms
		Eh	70 ms
		Fh	75 ms

5.6.1.8 VGL (07h)

The VGL register can be written to and read from.

Figure 5-31 VGL Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented				VGL
				R/W-1	R/W-0	R/W-0	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-11 VGL Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	VGL		These bits determine the output voltage of the negative charge pump (V_GL).
		0h	–5.0 V
		1h	–5.2 V
		2h	–5.4 V
		3h	–5.6 V
		4h	–5.8 V
		5h	–6.0 V
		6h	–6.2 V
		7h	–6.4 V
		8h	–6.6 V
		9h	–6.8 V
		Ah	–7.0 V
		Bh	–7.2 V
		Ch	–7.4 V
		Dh	–7.6 V
		Eh	–7.8 V
		Fh	–8.0 V

5.6.1.9 SS3 (08h)

The SS3 register can be written to and read from.

Figure 5-32 SS3 Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented					SS3
					R/W-0	R/W-0	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-12 SS3 Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	SS3		These bits determine the soft-start time of the negative charge pump (V_GL).
		0h	0.256 ms
		1h	5 ms
		2h	10 ms
		3h	15 ms
		4h	20 ms
		5h	25 ms
		6h	30 ms
		7h	35 ms

5.6.1.10 DLY3 (09h)

The DLY3 register can be written to and read from.

Figure 5-33 DLY3 Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented					DLY3
					R/W-0	R/W-0	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-13 DLY3 Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	DLY3		These bits determine how soon after boost converter 1 (AV_DD) starts the negative charge pump (V_GL) starts.
		0h	0 ms
		1h	5 ms
		2h	10 ms
		3h	15 ms
		4h	20 ms
		5h	25 ms
		6h	30 ms
		7h	35 ms

5.6.1.11 VGH (0Ah)

The VGH register can be written to and read from.

Figure 5-34 VGH Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented				VGH
				R/W-0	R/W-1	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-14 VGH Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	VGH		These bits determine the output voltage of boost converter 2 (V_GH).
		0h	18.0 V
		1h	18.5 V
		2h	19.0 V
		3h	19.5 V
		4h	20.0 V
		5h	20.5 V
		6h	21.0 V
		7h	21.5 V
		8h	22 0 V
		9h	22.5 V
		Ah	23.0 V
		Bh	23.5 V
		Ch	24.0 V
		Dh	24.5 V
		Eh	25.0 V
		Fh	25.5 V

5.6.1.12 SS4 (0Bh)

The SS4 register can be written to and read from.

Figure 5-35 SS4 Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented					SS4
					R/W-0	R/W-0	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-15 SS4 Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	SS4		These bits determine the soft-start time of boost converter 2 (V_GH).
		0h	0.256 ms
		1h	5 ms
		2h	10 ms
		3h	15 ms
		4h	20 ms
		5h	25 ms
		6h	30 ms
		7h	35 ms

5.6.1.13 FSW3 (0Ch)

The FSW3 register can be written to and read from.

Figure 5-36 FSW3 Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented						FSW3
						R/W-0	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-16 FSW3 Register Field Descriptions

Bit	Field	Value	Description
7-2	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
1-0	FSW3		These bits determine the switching frequency of boost converter 3 (WLED).
		0h	400 kHz
		1h	600 kHz
		2h	800 kHz
		3h	1 MHz

5.6.1.14 DLY4 (0Dh)

The DLY4 register can be written to and read from.

Figure 5-37 DLY4 Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented					DLY4
					R/W-0	R/W-1	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-17 DLY4 Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	DLY4		These bits determine the start-up delay of the gate voltage shaping function.
		0h	0 ms
		1h	5 ms
		2h	10 ms
		3h	15 ms
		4h	20 ms
		5h	25 ms
		6h	30 ms
		7h	35 ms

5.6.1.15 OVP (0Eh)

The OVP register can be written to and read from.

Figure 5-38 OVP Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented						OVP
						R/W-1	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-18 OVP Register Field Descriptions

Bit	Field	Value	Description
7-2	Not implemented	N/A	These bits are not implemented. During write operations, data for these bits is ignored, and during read operations 0 is returned.
1-0	OVP		These bits determine the overvoltage threshold of boost converter 3 (WLED).
		0h	30 V
		1h	33 V
		2h	36 V
		3h	39 V

5.6.1.16 FDIM (OFh)

The FDIM register can be written to and read from.

Figure 5-39 FDIM Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented					FDIM
					R/W-1	R/W-1	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-19 FDIM Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	FDIM		These bits determine the WLED driver's output dimming frequency in phase-shift dimming mode.
		0h	15 kHz
		1h	16 kHz
		2h	17 kHz
		3h	18 kHz
		4h	19 kHz
		5h	20 kHz
		6h	21 kHz
		7h	22 kHz

5.6.1.17 RESET (10h)

The RESET register can be written to and read from.

Figure 5-40 RESET Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented				RESET
				R/W-0	R/W-1	R/W-0	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-20 RESET Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	RESET		These bits determine the duration of the reset pulse (RST).
		0h	0 ms
		1h	1 ms
		2h	2 ms
		3h	3 ms
		4h	4 ms
		5h	5 ms
		6h	6 ms
		7h	7 ms
		8h	8 ms
		9h	9 ms
		Ah	10 ms
		Bh	11 ms
		Ch	12 ms
		Dh	13 ms
		Eh	14 ms
		Fh	15 ms

5.6.1.18 VDET (11h)

The VDET register can be written to and read from.

Figure 5-41 VDET Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented				VDET
				R/W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-21 VDET Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	VDET		These bits determine the threshold voltage of the XAO signal.
		0h	V_UVLO
		1h	2.0 V
		2h	2.1 V
		3h	2.2 V
		4h	2.3 V
		5h	2.4 V
		6h	2.5 V
		7h	2.6 V
		8h	2.7 V
		9h	2.8 V
		Ah	2.9 V
		Bh	3.0 V
		Ch	3.0 V
		Dh	3.0 V
		Eh	3.0 V
		Fh	3.0 V

5.6.1.19 DLY6 (12h)

The DLY6 register can be written to and read from.

Figure 5-42 DLY6 Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented					DLY6
					R/W-0	R/W-1	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-22 DLY6 Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	DLY6		These bits determine the start-up delay time of the XAO signal.
		0h	0 ms
		1h	5 ms
		2h	10 ms
		3h	15 ms
		4h	20 ms
		5h	25 ms
		6h	30 ms
		7h	35 ms

5.6.1.20 VMAX (13h)

The VMAX register can be written to and read from.

Figure 5-43 VMAX Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented				VMAX
				R/W-0	R/W-1	R/W-1	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-23 VMAX Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	VMAX		These bits determine the maximum V_COM voltage.
		0h	2.5/8 × AV_DD
		1h	2.6/8 × AV_DD
		2h	2.7/8 × AV_DD
		3h	2.8/8 × AV_DD
		4h	2.9/8 × AV_DD
		5h	3.0/8 × AV_DD
		6h	3.1/8 × AV_DD
		7h	3.2/8 × AV_DD
		8h	3.3/8 × AV_DD
		9h	3.4/8 × AV_DD
		Ah	3.5/8 × AV_DD
		Bh	3.6/8 × AV_DD
		Ch	3.7/8 × AV_DD
		Dh	3.8/8 × AV_DD
		Eh	3.9/8 × AV_DD
		Fh	4.0/8 × AV_DD

5.6.1.21 VMIN (14h)

The VMIN register can be written to and read from.

Figure 5-44 VMIN Register Bit Allocation

7	6	5	4	3	2	1	0
Not Implemented				VMIN
				R/W-0	R/W-1	R/W-1	R/W-1

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-24 VMIN Register Field Descriptions

Bit	Field	Value	Description
7-4	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
3-0	VMIN		These bits determine the minimum V_COM voltage.
		0h	2.0/8 × AV_DD
		1h	2.1/8 × AV_DD
		2h	2.2/8 × AV_DD
		3h	2.3/8 × AV_DD
		4h	2.4/8 × AV_DD
		5h	2.5/8 × AV_DD
		6h	2.6/8 × AV_DD
		7h	2.7/8 × AV_DD
		8h	2.8/8 × AV_DD
		9h	2.9/8 × AV_DD
		Ah	3.0/8 × AV_DD
		Bh	3.1/8 × AV_DD
		Ch	3.2/8 × AV_DD
		Dh	3.3/8 × AV_DD
		Eh	3.4/8 × AV_DD
		Fh	3.5/8 × AV_DD

5.6.1.22 USER (15h)

The USER register can be written to and read from.

Figure 5-45 USER Register Bit Allocation

7	6	5	4	3	2	1	0
USER
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-25 USER Register Field Descriptions

Bit	Field	Value	Description
7-0	USER	N/A	These bits are free for customer use. Their contents have no effect on device operation.

5.6.1.23 CONTROL (FFh)

Figure 5-46 CONTROL Register Bit Allocation

7	6	5	4	3	2	1	0
WED	Not Implemented						RED
R/W-0							R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-26 CONTROL Register Field Descriptions

Bit	Field	Value	Description
7	WED		This bit determines whether write operations affect the contents of the volatile or non-volatile registers.
		0h	Not applicable (see below).
		1h	Data is copied from the RAM registers to the EEPROM registers. This bit is automatically reset upon completion of this task.
6-1	Not Implemented	N/A	These bits are not implemented. During write operations data for these bits is ignored, and during read operations 0 is returned.
0	RED		This bit determines whether read operations return the contents of the volatile or non-volatile registers.
		0h	Volatile register data is returned.
		1h	Non-volatile register data is returned.

5.6.2 VCOM Registers

5.6.2.1 VCOM DATA (Slave Address 28h, Register Address 00h)

The VCOM DATA register can be written to and read from.

Figure 5-47 VCOM DATA Register Bit Allocation

7	6	5	4	3	2	1	0
NI	VCOM
R-0	R/W-1	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-27 VCOM DATA Register Bit Description

Bit	Field	Value	Description
7	Not implemented	N/A	This bit is reserved for future use and should be programmed to 0 for proper operation.
6-0	VCOM		Bits 6 through 0 set the value of the V_COM voltage.
6-0	VCOM	N/A	V_COM=(VCOM/127) × (V_MAX–V_MIN) + V_MIN

5.6.2.2 VCOM CONTROL (Slave Address 28h, Register Address 02h)

The VCOM CONTROL register is write-only.

Figure 5-48 VCOM CONTROL Register Bit Allocation

7	6	5	4	3	2	1	0
SEL	Not Implemented
R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0	R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n = factory default

Table 5-28 VCOM CONTROL Register Bit Description

Bit	Field	Value	Description
7	SEL		The SEL bit determines whether read/write operations to the VCOM DATA register access the IVR, the WR, or both.
		0	Write operations store data in the IVR and WR. Read operations return the contents of the IVR.
		1	Write operations store data in the WR only. Read operations return the contents of the WR.
6-0	Not implemented	N/A	Bits 6 through 0 are reserved for future use. They should be programmed to 0 for proper operation.

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5 Detailed Description

5.1 Overview

5.2 Functional Block Diagram

5.3 Feature Description

5.3.1 Linear Regulator (VCC)

5.3.1.1 Power-Up (Linear Regulator)

5.3.1.2 Power-Down (Linear Regulator)

5.3.1.3 Protection (Linear Regulator)

5.3.2 Boost Converter 1 (AVDD)

5.3.2.1 Power-Up (Boost Converter 1)

5.3.2.2 Power-Down (Boost Converter 1)

5.3.2.3 Protection (Boost Converter 1)

5.3.3 Boost Converter 2 (VGH)

5.3.3.1 Power-Up (Boost Converter 2)

5.3.3.2 Power-Down (Boost Converter 2)

5.3.3.3 Protection (Boost Converter 2)

5.3.4 Negative Charge Pump (VGL)

5.3.4.1 Power-Up (Negative Charge Pump)

5.3.4.2 Power-Down (Negative Charge Pump)

5.3.4.3 Protection (Negative Charge Pump)

5.3.5 Gate Voltage Shaping

5.3.6 Panel Discharge (XAO)

5.3.7 Reset Generator (RST)

5.3.8 Programmable VCOM

Table 5-1 Programmable VCOM Register Address Map

5.3.8.1 Operational Amplifier Performance

5.3.8.2 Power-Up (Programmable VCOM)

5.3.8.3 Power-Down (Programmable VCOM)

5.3.9 WLED Driver

5.3.9.1 WLED Boost Converter

5.3.9.2 Current Sinks

5.3.9.3 Protection

Table 5-2 WLED Driver Protection

5.3.9.4 Enable and Start-Up

5.3.10 Undervoltage Lockout

5.4 Device Functional Modes

5.4.1 Dimming Modes

5.4.1.1 Direct Dimming

5.4.1.2 Phase-Shift Dimming

5.4.2 Power Sequencing

5.4.2.1 Power-Up

5.4.2.2 Power-Down

5.5 Programming

5.5.1 Configuration

5.5.1.1 General

5.5.1.1.1 I2C Interface

5.5.1.1.2 Slave Addresses

5.5.1.1.3 Write Protect

5.5.2 Programming Examples (Excluding VCOM)

5.5.2.1 Writing to a Single RAM Register

5.5.2.2 Writing to Multiple RAM Registers

5.5.2.3 Saving Contents of all RAM Registers to EEPROM

5.5.2.4 Reading from a Single RAM Register

5.5.2.5 Reading from a Single EEPROM Register

5.5.2.6 Reading from Multiple RAM Registers

5.5.2.7 Reading from Multiple EEPROM Registers

5.5.3 Programming Examples - VCOM

5.5.3.1 Writing a VCOM Value of 77h to WR

5.5.3.2 Writing a VCOM Value of 77h to IVR and WR

5.5.3.3 Reading a VCOM Value of 77h from WR

5.5.3.4 Reading a VCOM Value of 77h from IVR

5.6 Register Map

5.6.1 Configuration Registers (Excluding VCOM)

Table 5-3 Configuration Memory Map

5.6.1.1 CONFIG (00h)

Table 5-4 CONFIG Register Field Descriptions

5.6.1.2 VCC (01h)

Table 5-5 VCC Register Field Descriptions

5.6.1.3 DLY1 (02h)

Table 5-6 DLY1 Register Field Descriptions

5.6.1.4 AVDD (03h)

Table 5-7 AVDD Register Field Descriptions

5.6.1.5 FSW1 (04h)

Table 5-8 FSW1 Register Field Descriptions

5.6.1.6 SS2 (05h)

Table 5-9 SS2 Register Field Descriptions

5.3.1 Linear Regulator (V_CC)

5.3.2 Boost Converter 1 (AV_DD)

5.3.3 Boost Converter 2 (V_GH)

5.3.4 Negative Charge Pump (V_GL)

5.5.1.1.1 I²C Interface