ZHCSF63A September   2013  – June 2016 TPS65154

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3. 1.3 说明
    4. 1.4 简化系统图
  2. 2 修订历史记录
  3. 3 Pin Configuration and Functions
  4. 4 Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Thermal Information
    5. 4.5 Electrical Characteristics
    6. 4.6 Timing Requirements
  5. 5 Detailed Description
    1. 5.1 Overview
    2. 5.2 Functional Block Diagram
    3. 5.3 Feature Description
      1. 5.3.1  Linear Regulator (VCC)
        1. 5.3.1.1 Power-Up (Linear Regulator)
        2. 5.3.1.2 Power-Down (Linear Regulator)
        3. 5.3.1.3 Protection (Linear Regulator)
      2. 5.3.2  Boost Converter 1 (AVDD)
        1. 5.3.2.1 Power-Up (Boost Converter 1)
        2. 5.3.2.2 Power-Down (Boost Converter 1)
        3. 5.3.2.3 Protection (Boost Converter 1)
      3. 5.3.3  Boost Converter 2 (VGH)
        1. 5.3.3.1 Power-Up (Boost Converter 2)
        2. 5.3.3.2 Power-Down (Boost Converter 2)
        3. 5.3.3.3 Protection (Boost Converter 2)
      4. 5.3.4  Negative Charge Pump (VGL)
        1. 5.3.4.1 Power-Up (Negative Charge Pump)
        2. 5.3.4.2 Power-Down (Negative Charge Pump)
        3. 5.3.4.3 Protection (Negative Charge Pump)
      5. 5.3.5  Gate Voltage Shaping
      6. 5.3.6  Panel Discharge (XAO)
      7. 5.3.7  Reset Generator (RST)
      8. 5.3.8  Programmable VCOM
        1. 5.3.8.1 Operational Amplifier Performance
        2. 5.3.8.2 Power-Up (Programmable VCOM)
        3. 5.3.8.3 Power-Down (Programmable VCOM)
      9. 5.3.9  WLED Driver
        1. 5.3.9.1 WLED Boost Converter
        2. 5.3.9.2 Current Sinks
        3. 5.3.9.3 Protection
        4. 5.3.9.4 Enable and Start-Up
      10. 5.3.10 Undervoltage Lockout
    4. 5.4 Device Functional Modes
      1. 5.4.1 Dimming Modes
        1. 5.4.1.1 Direct Dimming
        2. 5.4.1.2 Phase-Shift Dimming
      2. 5.4.2 Power Sequencing
        1. 5.4.2.1 Power-Up
        2. 5.4.2.2 Power-Down
    5. 5.5 Programming
      1. 5.5.1 Configuration
        1. 5.5.1.1 General
          1. 5.5.1.1.1 I2C Interface
          2. 5.5.1.1.2 Slave Addresses
          3. 5.5.1.1.3 Write Protect
      2. 5.5.2 Programming Examples (Excluding VCOM)
        1. 5.5.2.1 Writing to a Single RAM Register
        2. 5.5.2.2 Writing to Multiple RAM Registers
        3. 5.5.2.3 Saving Contents of all RAM Registers to EEPROM
        4. 5.5.2.4 Reading from a Single RAM Register
        5. 5.5.2.5 Reading from a Single EEPROM Register
        6. 5.5.2.6 Reading from Multiple RAM Registers
        7. 5.5.2.7 Reading from Multiple EEPROM Registers
      3. 5.5.3 Programming Examples - VCOM
        1. 5.5.3.1 Writing a VCOM Value of 77h to WR
        2. 5.5.3.2 Writing a VCOM Value of 77h to IVR and WR
        3. 5.5.3.3 Reading a VCOM Value of 77h from WR
        4. 5.5.3.4 Reading a VCOM Value of 77h from IVR
    6. 5.6 Register Map
      1. 5.6.1 Configuration Registers (Excluding VCOM)
        1. 5.6.1.1  CONFIG (00h)
        2. 5.6.1.2  VCC (01h)
        3. 5.6.1.3  DLY1 (02h)
        4. 5.6.1.4  AVDD (03h)
        5. 5.6.1.5  FSW1 (04h)
        6. 5.6.1.6  SS2 (05h)
        7. 5.6.1.7  DLY2 (06h)
        8. 5.6.1.8  VGL (07h)
        9. 5.6.1.9  SS3 (08h)
        10. 5.6.1.10 DLY3 (09h)
        11. 5.6.1.11 VGH (0Ah)
        12. 5.6.1.12 SS4 (0Bh)
        13. 5.6.1.13 FSW3 (0Ch)
        14. 5.6.1.14 DLY4 (0Dh)
        15. 5.6.1.15 OVP (0Eh)
        16. 5.6.1.16 FDIM (OFh)
        17. 5.6.1.17 RESET (10h)
        18. 5.6.1.18 VDET (11h)
        19. 5.6.1.19 DLY6 (12h)
        20. 5.6.1.20 VMAX (13h)
        21. 5.6.1.21 VMIN (14h)
        22. 5.6.1.22 USER (15h)
        23. 5.6.1.23 CONTROL (FFh)
      2. 5.6.2 VCOM Registers
        1. 5.6.2.1 VCOM DATA (Slave Address 28h, Register Address 00h)
        2. 5.6.2.2 VCOM CONTROL (Slave Address 28h, Register Address 02h)
  6. 6 Application and Implementation
    1. 6.1 Application Information
    2. 6.2 Typical Application
      1. 6.2.1 Design Requirements
      2. 6.2.2 Detailed Design Procedure
        1. 6.2.2.1 External Component Selection
      3. 6.2.3 Application Curves
  7. 7 Power Supply Recommendations
  8. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  9. 9 器件和文档支持
    1. 9.1 器件支持
      1. 9.1.1 Third-Party Products Disclaimer
    2. 9.2 接收文档更新通知
    3. 9.3 社区资源
    4. 9.4 商标
    5. 9.5 静电放电警告
    6. 9.6 Glossary
  10. 10机械、封装和可订购信息
    1. 10.1 封装信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8 Layout

8.1 Layout Guidelines

The PCB layout is an important step in a power supply design. An incorrect layout can cause converter instability, load regulation problems, noise, and EMI issues. The list of recommendations below highlights the most important points to consider when doing the layout for the TPS65154 device. However, all PCB layout is a trade-off between theory and practice, and some compromise is always necessary.

  • If possible, use a 4-layer PCB. Route high di/dt signals on layer 1 and use the second layer to form a solid ground plane. If a 2-layer PCB is used, route high di/dt signals on layer 1 and add a copper pour connected to ground on the bottom layer.
  • Place a decoupling capacitor close to the VIN pin. Use short, wide traces on layer 1 to connect to it.
  • Place at least one of the boost converter 1 output capacitors close to the device. Use short, wide traces on layer 1 to connect it between pins 3 and 4, and pin 6.
  • Place the boost converter 3 rectifier diode and output capacitor close to the device. Use short, wide traces on layer 1 to connect them to pins 9 and 10.
  • Place the boost converter 2 rectifier diode and output capacitor close to the device. Use short, wide traces on layer 1 to connect them to pins 33 and 34.
  • Place the flying capacitor connected to pins 19 and 20 and the output capacitor connected to pin 18 close to the device. Use short, wide traces on layer 1 to connect to them.
  • Place the VCOM buffer decoupling capacitor connected between pin 2 and pin 47 close to the device. Use short, wide traces on layer 1 to connect to it.
  • Route the signals to the compensation components connected to pin 7, pin 40 and pin 46 away from noisy signals.
  • Use thermal vias to connect the thermal pad to a large, unbroken copper ground plane (typically, on layer 2).

8.2 Layout Example

Figure 8-1 shows the main features of the TPS65154 Evaluation Module PCB layout.

TPS65154 PCB_Layout_SLVSBG2.gif Figure 8-1 Example PCB Layout
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