米6体育平台手机版

ZHCSIX2 October 2018 TPS65216

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

RSL|48
- MPQF193A

散热焊盘机械数据 (封装 | 引脚)

RSL|48
- QFND155N

订购信息

3.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
INPUT VOLTAGE AND CURRENTS
V_{IN_BIAS}	Input supply voltage range	Normal operation		3.6		5.5	V
V_{IN_BIAS}	Input supply voltage range	EEPROM programming		4.5		5.5	V
	Deglitch time				5		ms
I_OFF	OFF state current, total current into IN_BIAS, IN_DCDCx, IN_LDO1, IN_LS	V_IN = 3.6 V; All rails disabled. T_J = 0°C to 85°C			5		µA
I_SUSPEND	SUSPEND current, total current into IN_BIAS, IN_DCDCx, IN_LDO1, IN_LS	V_IN = 3.6 V; DCDC3 enabled, low-power mode, no load. All other rails disabled. T_J = 0°C to 105°C			220		µA
INT_LDO
V_{INT_LDO}	Output voltage				2.5		V
V_{INT_LDO}	DC accuracy	I_OUT < 10 mA		–2%		2%
I_OUT	Output current range	Maximum allowable external load		0		10	mA
I_LIMIT	Short circuit current limit	Output shorted to GND			23		mA
t_HOLD	Hold-up time	Measured from V_{INT_LDO} = to V_{INT_LDO} = 1.8 V All rails enabled before power off, V_{IN_BIAS} = 2.8 V to 0 V in < No external load on INT_LDO C_{INT_LDO} = , see Table 5-3		150			ms
C_OUT	Nominal output capacitor value	Ceramic, X5R or X7R, see Table 5-3		0.1	1	22	µF
C_OUT	Tolerance	Ceramic, X5R or X7R, rated voltage ≥ 6.3 V		–20%		20%
DCDC1 (1.1-V BUCK)
V_{IN_DCDC1}	Input voltage range	V_{IN_BIAS} > V_UVLO		3.6		5.5	V
V_DCDC1	Output voltage range	Adjustable through I²C		0.85		1.675	V
V_DCDC1	DC accuracy	3.6 V ≤ V_IN ≤ 5.5 V; 0 A ≤ I_OUT ≤ 1.8 A		–2%		2%
	Dynamic accuracy	In respect to nominal output voltage I_OUT = 50 mA to 450 mA in < 1 µs C_OUT ≥ 10 µF, over full input voltage range		–2.5%		2.5%
I_OUT	Continuous output current	V_{IN_DCDC1} > 3.6 V				1.8	A
I_Q	Quiescent current	Total current from I_{N_DCDC1} pin; Device not switching, no load			25	50	µA
R_DS(ON)	High-side FET on resistance	V_{IN_DCDC1} = 3.6 V			230	355	mΩ
R_DS(ON)	Low-side FET on resistance	V_{IN_DCDC1} = 3.6 V			90	145	mΩ
I_LIMIT	High-side current limit	V_{IN_DCDC1} = 3.6 V			2.8		A
I_LIMIT	Low-side current limit	V_{IN_DCDC1} = 3.6 V			3.1		A
V_PG	Power-good threshold	V_OUT falling	STRICT = 0b	88.5%	90%	91.5%
	Power-good threshold	V_OUT falling	STRICT = 1b	96%	96.5%	97%
	Hysteresis	V_OUT rising	STRICT = 0b	3.8%	4.1%	4.4%
	Hysteresis	V_OUT rising	STRICT = 1b		0.25%
	Deglitch	V_OUT falling	STRICT = 0b		1		ms
		V_OUT falling	STRICT = 1b		50		µs
		V_OUT rising	STRICT = 0b		10		µs
		V_OUT rising	STRICT = 1b		10		µs
	Time-out				5		ms
V_OV	Overvoltage detection threshold	V_OUT rising, STRICT = 1b		103%	103.5%	104%
	Hysteresis	V_OUT falling, STRICT = 1b			0.25%
	Deglitch	V_OUT rising, STRICT = 1b			50		µs
I_INRUSH	Inrush current	V_{IN_DCDC1} = 3.6 V; C_OUT = 10 µF to 100 µF				500	mA
R_DIS	Discharge resistor			150	250	350	Ω
L	Nominal inductor value	See Table 5-2		1	1.5	2.2	µH
L	Tolerance			–30%		30%
C_OUT	Output capacitance value	Ceramic, X5R or X7R, see Table 5-3		10	22	100⁽⁵⁾	µF
DCDC2 (1.1-V BUCK)
V_{IN_DCDC2}	Input voltage range	V_{IN_BIAS} > V_UVLO		3.6		5.5	V
V_DCDC2	Output voltage range	Adjustable through I²C		0.85		1.675	V
V_DCDC2	DC accuracy	3.6 V ≤ V_IN ≤ 5.5 V; 0 A ≤ I_OUT ≤ 1.8 A		–2%		2%
	Dynamic accuracy	In respect to nominal output voltage I_OUT = 50 mA to 450 mA in < 1 µs C_OUT ≥ 10 µF, over full input voltage range		–2.5%		2.5%
I_OUT	Continuous output current	V_{IN_DCDC2} > 3.6 V				1.8	A
I_Q	Quiescent current	Total current from I_{N_DCDC2} pin; Device not switching, no load			25	50	µA
R_DS(ON)	High-side FET on resistance	V_{IN_DCDC2} = 3.6 V			230	355	mΩ
R_DS(ON)	Low-side FET on resistance	V_{IN_DCDC2} = 3.6 V			90	145	mΩ
I_LIMIT	High-side current limit	V_{IN_DCDC2} = 3.6 V			2.8		A
I_LIMIT	Low-side current limit	V_{IN_DCDC2} = 3.6 V			3.1		A
V_PG	Power-good threshold	V_OUT falling	STRICT = 0b	88.5%	90%	91.5%
	Power-good threshold	V_OUT falling	STRICT = 1b	96%	96.5%	97%
	Hysteresis	V_OUT rising	STRICT = 0b	3.8%	4.1%	4.4%
	Hysteresis	V_OUT rising	STRICT = 1b		0.25%
	Deglitch	V_OUT falling	STRICT = 0b		1		ms
		V_OUT falling	STRICT = 1b		50		µs
		V_OUT rising	STRICT = 0b		10		µs
		V_OUT rising	STRICT = 1b		10		µs
	Time-out	Occurs at enable of DCDC2 and after DCDC2 register write (register 0x17)			5		ms
V_OV	Overvoltage detection threshold	V_OUT rising, STRICT = 1b		103%	103.5%	104%
	Hysteresis	V_OUT falling, STRICT = 1b			0.25%
	Deglitch	V_OUT rising, STRICT = 1b			50		µs
I_INRUSH	Inrush current	V_{IN_DCDC2} = 3.6 V; C_OUT = 10 µF to 100 µF				500	mA
R_DIS	Discharge resistor			150	250	350	Ω
L	Nominal inductor value	See Table 5-2		1	1.5	2.2	µH
L	Tolerance			–30%		30%
C_OUT	Output capacitance value	Ceramic, X5R or X7R, see Table 5-3		10	22	100⁽⁵⁾	µF
DCDC3 (1.2-V BUCK)
V_{IN_DCDC3}	Input voltage range	V_{IN_BIAS} > V_UVLO		3.6		5.5	V
V_DCDC3	Output voltage range	Adjustable through I²C		0.9		3.4	V
V_DCDC3	DC accuracy	3.6 V ≤ V_IN ≤ 5.5 V; 0 A ≤ I_OUT ≤ 1.8 A, V_{IN_DCDC3} ≥ (V_DCDC3 + 700 mV)		–2%		2%
	Dynamic accuracy	In respect to nominal output voltage I_OUT = 50 mA to 450 mA in < 1 µs C_OUT ≥ 10 µF, over full input voltage range		–2.5%		–2.5%
I_OUT	Continuous output current	V_{IN_DCDC3} > 3.6 V				1.8	A
I_Q	Quiescent current	Total current from IN_DCDC3 pin; Device not switching, no load			25	50	µA
R_DS(ON)	High-side FET on resistance	V_{IN_DCDC3} = 3.6 V			230	345	mΩ
R_DS(ON)	Low-side FET on resistance	V_{IN_DCDC3} = 3.6 V			100	150	mΩ
I_LIMIT	High-side current limit	V_{IN_DCDC3} = 3.6 V			2.8		A
I_LIMIT	Low-side current limit	V_{IN_DCDC3} = 3.6 V			3		A
V_PG	Power-good threshold	V_OUT falling	STRICT = 0b	88.5%	90%	91.5%
	Power-good threshold	V_OUT falling	STRICT = 1b	95%	95.5%	96%
	Hysteresis	V_OUT rising	STRICT = 0b	3.8%	4.1%	4.4%
	Hysteresis	V_OUT rising	STRICT = 1b		0.25%
	Deglitch	V_OUT falling	STRICT = 0b		1		ms
		V_OUT falling	STRICT = 1b		50		µs
		V_OUT rising	STRICT = 0b		10		µs
		V_OUT rising	STRICT = 1b		10		µs
	Time-out	Occurs at enable of DCDC3 and after DCDC3 register write (register 0x18)			5		ms
V_OV	Overvoltage detection threshold	V_OUTrising, STRICT = 1b		104%	104.5%	105%
	Hysteresis	V_OUTfalling, STRICT = 1b			0.25%
	Deglitch	V_OUTrising, STRICT = 1b			50		µs
I_INRUSH	Inrush current	V_{IN_DCDC3} = 3.6 V; C_OUT = 10 µF to 100 µF				500	mA
R_DIS	Discharge resistor			150	250	350	Ω
L	Nominal inductor value	See Table 5-2		1.0	1.5	2.2	µH
L	Tolerance			–30%		30%
C_OUT	Output capacitance value	Ceramic, X5R or X7R, see Table 5-3		10	22	100	µF
DCDC4 (3.3-V BUCK-BOOST) / ANALOG AND I/O
V_{IN_DCDC4}	Input voltage operating range	V_{IN_BIAS} > V_UVLO, –40°C to +105°C		3.6		5.5	V
V_DCDC4	Output voltage range	Adjustable through I²C		1.175		3.3	V
V_DCDC4	DC accuracy	4.2 V ≤ V_IN ≤ 5.5 V; 3 V < V_OUT ≤ 3.4 V 0 A ≤ I_OUT ≤ 1.6 A		–2%		2%
		3.3 V ≤ V_IN ≤ 4.2 V; 3 V < V_OUT ≤ 3.4 V 0 A ≤ I_OUT ≤ 1.3 A		–2%		2%
		2.8 V ≤ V_IN ≤ 5.5 V; 1.65 V < V_OUT ≤ 3 V 0 A ≤ I_OUT ≤ 1 A		–2%		2%
		2.8 V ≤ V_IN ≤ 5.5 V; 1.175 V < V_OUT ≤ 1.65 V 0 A ≤ I_OUT ≤ 1 A		–2.5%		2.5%
	Output voltage ripple	PFM mode enabled; 4.2 V ≤ V_IN ≤ 5.5 V; 0 A ≤ I_OUT ≤ V_OUT = 3.3 V					mV_pp
	Minimum duty cycle in step-down mode					18%
I_OUT	Continuous output current	V_{IN_DCDC4} = 2.8 V, V_OUT = 3.3 V				1	A
		V_{IN_DCDC4} = 3.6 V, V_OUT = 3.3 V				1.3
		V_{IN_DCDC4} = 5 V, V_OUT = 3.3 V				1.6
I_Q	Quiescent current	Total current from IN_DCDC4 pin; Device not switching, no load			25	50	µA
f_SW	Switching frequency				2400		kHz
R_DS(ON)	High-side FET on resistance	V_{IN_DCDC3} = 3.6 V	IN_DCDC4 to L4A		166		mΩ
	High-side FET on resistance	V_{IN_DCDC3} = 3.6 V	L4B to DCDC4		149
	Low-side FET on resistance	V_{IN_DCDC3} = 3.6 V	L4A to GND		142	190
	Low-side FET on resistance	V_{IN_DCDC3} = 3.6 V	L4B to GND		144	190
I_LIMIT	Average switch current limit	V_{IN_DCDC4} = 3.6 V			3000		mA
V_PG	Power-good threshold	V_OUT falling	STRICT = 0b	88.5%	90%	91.5%
	Power-good threshold	V_OUT falling	STRICT = 1b	95%	95.5%	96%
	Hysteresis	V_OUT rising	STRICT = 0b	3.8%	4.1%	4.4%
	Hysteresis	V_OUT rising	STRICT = 1b		0.25%
	Deglitch	V_OUT falling	STRICT = 0b		1		ms
		V_OUT falling	STRICT = 1b		50		µs
		V_OUT rising	STRICT = 0b		10		µs
		V_OUT rising	STRICT = 1b		10		µs
	Time-out	Occurs at enable of DCDC4 and after DCDC4 register write (register 0x19)			5		ms
V_OV	Overvoltage detection threshold	V_OUT rising, STRICT = 1b		104%	104.5%	105%
	Hysteresis	V_OUT falling, STRICT = 1b			0.25%
	Deglitch	V_OUT rising, STRICT = 1b			50		µs
I_INRUSH	Inrush current	V_{IN_DCDC4} = 3.6 V ≤ V_INDCDC4 ≤ 5.5 V; 40 µF ≤ C_OUT ≤ 100 µF				500	mA
R_DIS	Discharge resistor			150	250	350	Ω
L	Nominal inductor value	See Table 5-2		1.2	1.5	2.2	µH
L	Tolerance			–30%		30%
C_OUT	Output capacitance value	Ceramic, X5R or X7R, see Table 5-3		40	80	100	µF
LDO1 (1.8-V LDO)
V_{IN_LDO1}	Input voltage range	V_{IN_BIAS} > V_UVLO		1.8		5.5	V
I_Q	Quiescent current	No load			35		µA
V_OUT	Output voltage range	Adjustable through I²C		0.9		3.4	V
V_OUT	DC accuracy	V_OUT + 0.2 V ≤ V_IN ≤ 5.5 V; 0 A ≤ I_OUT ≤ 200 mA		–2%		2%
I_OUT	Output current range	V_{IN_LDO1} – V_DO = V_OUT		0		200	mA
I_OUT	Output current range	V_{IN_LDO1} > 2.7 V, V_OUT = 1.8 V		0		400	mA
I_LIMIT	Short circuit current limit	Output shorted to GND		445	550		mA
V_DO	Dropout voltage	I_OUT = 100 mA, V_IN = 3.6 V				200	mV
V_PG	Power-good threshold	V_OUT falling	STRICT = 0b	86%	90%	94%
		V_OUT falling	STRICT = 1b	95%	95.5%	96%
		Hysteresis, V_OUT rising	STRICT = 0b	3%	4%	5%
		Hysteresis, V_OUT rising	STRICT = 1b		0.25%
	Deglitch	V_OUT falling	STRICT = 0b		1		ms
		V_OUT falling	STRICT = 1b		50		µs
		V_OUT rising	STRICT = 0b		10		µs
		V_OUT rising	STRICT = 1b		10		µs
	Time-out				5		ms
V_OV	Overvoltage detection threshold	V_OUT rising, STRICT = 1b		104%	104.5%	105%
	Hysteresis	V_OUT falling, STRICT = 1b			0.25%
	Deglitch	V_OUT rising, STRICT = 1b			50		µs
	Deglitch	V_OUT falling, STRICT = 1b			1		ms
R_DIS	Discharge resistor			150	250	380	Ω
C_OUT	Output capacitance value	Ceramic, X5R or X7R			22	100	µF
LOAD SWITCH
V_{IN_LS}	Input voltage range	V_{IN_BIAS} > V_UVLO		1.8		10	V
R_DS(ON)	Static on resistance	V_{IN_LS} = 9 V, I_OUT= 500 mA, over full temperature range				440	mΩ
		V_{IN_LS} = 5 V, I_OUT= 500 mA, over full temperature range				526
		V_{IN_LS} = 2.8 V, I_OUT= 200 mA, over full temperature range				656
		V_{IN_LS} = 1.8 V, I_OUT= 200 mA, over full temperature range				910
I_LIMIT	Short circuit current limit	V_{IN_LS} > 2.3 V, Output shorted to GND	LSILIM[1:0] = 00b	98		126	mA
			LSILIM[1:0] = 01b	194		253
			LSILIM[1:0] = 10b	475		738
			LSILIM[1:0] = 11b	900		1234
		V_{IN_LS} ≤ 2.3 V, Output shorted to GND	LSILIM[1:0] = 00b	98		126
			LSILIM[1:0] = 01b	194		253
			LSILIM[1:0] = 10b	475		738
t_BLANK	Interrupt blanking time	Output shorted to GND until interrupt is triggered			15		ms
R_DIS	Internal discharge resistor at output⁽¹⁾	LSDCHRG = 1		650	1000	1500	Ω
T_OTS	Overtemperature shutdown⁽²⁾			125	132	139	°C
T_OTS	Hysteresis				10		°C
C_OUT	Nominal output capacitance value	Ceramic, X5R or X7R, see Table 5-3		1	100	220	µF
I/O LEVELS AND TIMING CHARACTERISTICS
PG_DLY	PGOOD delay time	PGDLY[1:0] = 00b			10		ms
		PGDLY[1:0] = 01b			20
		PGDLY[1:0] = 10b			50
		PGDLY[1:0] = 11b			150
t_DG	Deglitch time	PB input	Rising edge		100		ms
		PB input	Falling edge		50		ms
		AC_DET input	Rising edge		100		µs
		AC_DET input	Falling edge		10		ms
		PWR_EN input	Rising edge		10		ms
		PWR_EN input	Falling edge		100		µs
		GPIO1	Rising edge		1		ms
		GPIO1	Falling edge		1		ms
		GPIO2	Rising edge		5		µs
		GPIO2	Falling edge		5		µs
t_RESET	Reset time	PB input held low	TRST = 0b		8		s
t_RESET	Reset time	PB input held low	TRST = 1b		15		s
V_IH	High level input voltage	SCL, SDA, GPIO1, GPIO2		1.3			V
		AC_DET, PB		0.66 × IN_BIAS
		PWR_EN		1.3
V_IL	Low level input voltage	SCL, SDA, PWR_EN, AC_DET, PB, GPIO1, GPIO2		0		0.4	V
V_OL	Low level output voltage	nWAKEUP, nINT, SDA, PGOOD, GPIO1, GPIO2; I_SINK = 2 mA		0		0.3	V
V_OL	Low level output voltage	nPFO; I_SINK = 2 mA		0		0.35	V
V_PFI	Power-fail comparator threshold	Input falling			800		mV
	Hysteresis	Input rising			40		mV
	Accuracy			–4%		4%
	Deglitch	Input falling			25		µs
	Deglitch	Input rising			10		ms
I_{DC34_SEL}	DC34_SEL bias current	Enabled only at power-up			10		µA
V_{DC34_SEL}	DCDC3 / DCDC4 power-up default selection thresholds	Threshold 1			100		mV
		Threshold 2			163
		Threshold 3			275
		Threshold 4			400
		Threshold 5			575
		Threshold 6			825
		Threshold 7			1200
R_{DC34_SEL}	DCDC3 / DCDC4 power-up default selection resistor values	Setting 0		0	0	7.7	kΩ
		Setting 1			12.1
		Setting 2			20
		Setting 3		30.9	31.6	32.3
		Setting 4			45.3
		Setting 5
		Setting 6			95.3
		Setting 7			150
I_BIAS	Input bias current	SCL, SDA, GPIO1⁽³⁾, GPIO2⁽³⁾; V_IN = 3.3 V			0.01	1	µA
I_BIAS	Input bias current	PB, AC_DET, PFI; V_IN = 3.3 V				500	nA
I_LEAK	Pin leakage current	nINT, nWAKEUP, nPFO, PGOOD, PWR_EN, GPIO1⁽⁴⁾, GPIO2⁽⁴⁾ V_OUT = 3.3 V				500	nA
OSCILLATOR
ƒ_OSC	Oscillator frequency				2400		kHz
ƒ_OSC	Frequency accuracy	T_J = –40°C to +105°C		–12%		12%
T_OTS	Overtemperature shutdown	Increasing junction temperature		135	145	155	°C
T_OTS	Hysteresis	Decreasing junction temperature			20		°C
T_WARN	High-temperature warning	Increasing junction temperature		90	100	110	°C
T_WARN	Hysteresis	Decreasing junction temperature			15		°C

(1) Discharge function disabled by default.

(2) Switch is temporarily turned OFF if input voltage drops below UVLO threshold.

(3) Configured as input.

(4) Configured as output.

(5) 500-µF of remote capacitance can be supported for DCDC1/2.