ZHCSIX2
October 2018
TPS65216
PRODUCTION DATA.
1
器件概述
1.1
特性
1.2
应用
1.3
说明
1.4
简化原理图
2
Pin Configuration and Functions
2.1
Pin Functions
Pin Functions
3
Specifications
3.1
Absolute Maximum Ratings
3.2
ESD Ratings
3.3
Recommended Operating Conditions
3.4
Thermal Information
3.5
Electrical Characteristics
3.6
Timing Requirements
3.7
Typical Characteristics
4
Detailed Description
4.1
Overview
4.2
Functional Block Diagram
4.3
Feature Description
4.3.1
Wake-Up and Power-Up and Power-Down Sequencing
4.3.1.1
Power-Up Sequencing
4.3.1.2
Power-Down Sequencing
4.3.1.3
Strobes 1 and 2
4.3.1.4
Supply Voltage Supervisor and Power Good (PGOOD)
4.3.1.5
Internal LDO (INT_LDO)
4.3.1.6
Current Limited Load Switch
4.3.1.7
LDO1
4.3.1.8
UVLO
4.3.1.9
Power-Fail Comparator
4.3.1.10
DCDC3 / DCDC4 Power-Up Default Selection
4.3.1.11
I/O Configuration
4.3.1.11.1
Using GPIO2 as Reset Signal to DCDC1 and DCDC2
4.3.1.12
Push Button Input (PB)
4.3.1.12.1
Signaling PB-Low Event on the nWAKEUP Pin
4.3.1.12.2
Push Button Reset
4.3.1.13
AC_DET Input (AC_DET)
4.3.1.14
Interrupt Pin (INT)
4.3.1.15
I2C Bus Operation
4.4
Device Functional Modes
4.4.1
Modes of Operation
4.4.2
OFF
4.4.3
ACTIVE
4.4.4
SUSPEND
4.4.5
RESET
4.5
Register Maps
4.5.1
Password Protection
4.5.2
FLAG Register
4.5.3
TPS65216Registers
4.5.3.1
CHIPID Register (subaddress = 0x0) [reset = 0x5]
Table 4-7
CHIPID Register Field Descriptions
4.5.3.2
INT1 Register (subaddress = 0x1) [reset = 0x0]
Table 4-8
INT1 Register Field Descriptions
4.5.3.3
INT2 Register (subaddress = 0x2) [reset = 0x0]
Table 4-9
INT2 Register Field Descriptions
4.5.3.4
INT_MASK1 Register (subaddress = 0x3) [reset = 0x0]
Table 4-10
INT_MASK1 Register Field Descriptions
4.5.3.5
INT_MASK2 Register (subaddress = 0x4) [reset = 0x0]
Table 4-11
INT_MASK2 Register Field Descriptions
4.5.3.6
STATUS Register (subaddress = 0x5) [reset = 00XXXXXXb]
Table 4-12
STATUS Register Field Descriptions
4.5.3.7
CONTROL Register (subaddress = 0x6) [reset = 0x0]
Table 4-13
CONTROL Register Field Descriptions
4.5.3.8
FLAG Register (subaddress = 0x7) [reset = 0x0]
Table 4-14
FLAG Register Field Descriptions
4.5.3.9
PASSWORD Register (subaddress = 0x10) [reset = 0x0]
Table 4-15
PASSWORD Register Field Descriptions
4.5.3.10
ENABLE1 Register (subaddress = 0x11) [reset = 0x0]
Table 4-16
ENABLE1 Register Field Descriptions
4.5.3.11
ENABLE2 Register (subaddress = 0x12) [reset = 0x0]
Table 4-17
ENABLE2 Register Field Descriptions
4.5.3.12
CONFIG1 Register (subaddress = 0x13) [reset = 0x4C]
Table 4-18
CONFIG1 Register Field Descriptions
4.5.3.13
CONFIG2 Register (subaddress = 0x14) [reset = 0xC0]
Table 4-19
CONFIG2 Register Field Descriptions
4.5.3.14
CONFIG3 Register (subaddress = 0x15) [reset = 0x0]
Table 4-20
CONFIG3 Register Field Descriptions
4.5.3.15
DCDC1 Register (offset = 0x16) [reset = 0x99]
Table 4-21
DCDC1 Register Field Descriptions
4.5.3.16
DCDC2 Register (subaddress = 0x17) [reset = 0x99]
Table 4-22
DCDC2 Register Field Descriptions
4.5.3.17
DCDC3 Register (subaddress = 0x18) [reset = 0x8C]
Table 4-23
DCDC3 Register Field Descriptions
4.5.3.18
DCDC4 Register (subaddress = 0x19) [reset = 0xB2]
Table 4-24
DCDC4 Register Field Descriptions
4.5.3.19
SLEW Register (subaddress = 0x1A) [reset = 0x6]
Table 4-25
SLEW Register Field Descriptions
4.5.3.20
LDO1 Register (subaddress = 0x1B) [reset = 0x1F]
Table 4-26
LDO1 Register Field Descriptions
4.5.3.21
SEQ1 Register (subaddress = 0x20) [reset = 0x0]
Table 4-27
SEQ1 Register Field Descriptions
4.5.3.22
SEQ2 Register (subaddress = 0x21) [reset = 0x0]
Table 4-28
SEQ2 Register Field Descriptions
4.5.3.23
SEQ3 Register (subaddress = 0x22) [reset = 0x98]
Table 4-29
SEQ3 Register Field Descriptions
4.5.3.24
SEQ4 Register (subaddress = 0x23) [reset = 0x75]
Table 4-30
SEQ4 Register Field Descriptions
4.5.3.25
SEQ5 Register (subaddress = 0x24) [reset = 0x12]
Table 4-31
SEQ5 Register Field Descriptions
4.5.3.26
SEQ6 Register (subaddress = 0x25) [reset = 0x63]
Table 4-32
SEQ6 Register Field Descriptions
4.5.3.27
SEQ7 Register (subaddress = 0x26) [reset = 0x3]
Table 4-33
SEQ7 Register Field Descriptions
5
Application and Implementation
5.1
Application Information
5.2
Typical Application
5.2.1
Design Requirements
5.2.2
Detailed Design Procedure
5.2.2.1
Output Filter Design
5.2.2.2
Inductor Selection for Buck Converters
5.2.2.3
Output Capacitor Selection
5.2.3
Application Curves
6
Power Supply Recommendations
7
Layout
7.1
Layout Guidelines
7.2
Layout Example
8
器件和文档支持
8.1
器件支持
8.1.1
第三方米6体育平台手机版_好二三四免责声明
8.2
文档支持
8.2.1
相关文档
8.3
接收文档更新通知
8.4
社区资源
8.5
商标
8.6
静电放电警告
8.7
Glossary
9
机械、封装和可订购信息
9.1
Package Option Addendum
9.1.1
Packaging Information
9.1.2
Tape and Reel Information
封装选项
机械数据 (封装 | 引脚)
RSL|48
MPQF193A
散热焊盘机械数据 (封装 | 引脚)
RSL|48
QFND155N
订购信息
zhcsix2_oa
zhcsix2_pm
4.4.1
Modes of Operation
Figure 4-24
Modes of Operation Diagram
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