10.1 Layout Guidelines

As for all switching power supplies, the layout is an important step in the design. Proper function of the device requires careful attention to printed circuit-board (PCB) layout. Care must be taken in board layout to get the specified performance.

• The VIN_DCDCx and VINLDO pins should be bypassed to ground with a low-ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 10 μF and 4.7 μF with a X5R or X7R dielectric, respectively.
• The optimum placement of these bypass capacitors is close to the VIN_DCDCx and VINLDO pins of the TPS652170 device. Care should be taken to minimize the loop area formed by the bypass capacitor connection, the VIN_DCDCx and VINLDO pins, and the thermal pad of the device.
• The thermal pad should be tied to the PCB ground plane with multiple vias.
• The inductor traces from the Lx pins to the V_OUT node (VDCDCx) of each DCDCx converter should be kept on the PCB top layer and free of any vias.
• The VLDOx and VDCDCx pin (feedback pin labeled FB1 in Figure 78) traces should be routed away from any potential noise source to avoid coupling.
• The DCDCx output capacitance should be placed immediately at the DCDCx pin. Excessive distance between the capacitance and DCDCx pin may cause poor converter performance.