7.3.1.2 Power-Down Sequencing

By default, power-down sequencing follows the reverse power-up sequence. When the power-down sequence is triggered, STROBE7 occurs first, and any rail assigned to STROBE7 is shut down. After a delay time of DLY6, STROBE6 occurs, and any rail assigned to STROBE6 is shut down. The sequence continues until all strobes have occurred and all DLYx times have been executed.

In some applications, all rails may be required to shut down at the same time with no delay between rails. Set the INSTDWN bit in the SEQ6 register to bypass all delay times and shut-down all rails at the same time when the power-down sequence is triggered.

A power-down sequence is executed if one of the following events occurs:

• The SEQDWN bit is set.
• The PWR_EN pin is pulled low.
• The push-button is pressed for more than 8 s.
• The nRESET pin is pulled low.
• A fault occurs in the device (either an OTS, UVLO, or PGOOD failure).
• The PWR_EN pin is not asserted (pulled high) within 5 s of a power-up event and the OFF bit is set to 1b.

When the device goes from the ACTIVE to the OFF state, any rail not controlled by the sequencer is shut down after the power-down sequencer is complete. When the device goes from the ACTIVE to the SLEEP state, any rail not controlled by the power-down sequencer stays in its present state.

Figure 5. Power-Down Sequence from ON State to OFF State (All Rails Turned OFF)

STROBE14 and STROBE15 are omitted to let the LDO1 or LDO2 regulators stay ON.

Figure 6. Power-Down Sequence from ON State to SLEEP State