ZHCSJX9 June   2019 TPS652170

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用示意图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Wake-Up and Power-Up Sequencing
        1. 7.3.1.1 Power-Up Sequencing
        2. 7.3.1.2 Power-Down Sequencing
        3. 7.3.1.3 Special Strobes (STROBE 14 and 15)
      2. 7.3.2  Power Good
        1. 7.3.2.1 LDO1, LDO2 Power-Good (LDO_PGOOD)
        2. 7.3.2.2 Primary Power-Good (PGOOD)
        3. 7.3.2.3 Load Switch PGOOD
      3. 7.3.3  Push-Button Monitor (PB_IN)
      4. 7.3.4  nWAKEUP Pin (nWAKEUP)
      5. 7.3.5  Power Enable Pin (PWR_EN)
      6. 7.3.6  Reset Pin (nRESET)
      7. 7.3.7  Interrupt Pin (nINT)
      8. 7.3.8  Analog Multiplexer
      9. 7.3.9  Battery Charger and Power Path
        1. 7.3.9.1 Shorted or Absent Battery (VBAT < 1.5 V)
        2. 7.3.9.2 Dead Battery (1.5 V < VBAT < VUVLO)
        3. 7.3.9.3 Good Battery (VBAT > VUVLO)
        4. 7.3.9.4 AC and USB Input Discharge
      10. 7.3.10 Battery Charging
      11. 7.3.11 Precharge
      12. 7.3.12 Charge Termination
      13. 7.3.13 Battery Detection and Recharge
      14. 7.3.14 Safety Timer
        1. 7.3.14.1 Dynamic Timer Function
        2. 7.3.14.2 Timer Fault
      15. 7.3.15 Battery-Pack Temperature Monitoring
      16. 7.3.16 DC/DC Converters
        1. 7.3.16.1 Operation
        2. 7.3.16.2 Output Voltage Setting
        3. 7.3.16.3 Power-Save Mode and Pulse-Frequency Modulation (PFM)
        4. 7.3.16.4 Dynamic Voltage Positioning
        5. 7.3.16.5 100% Duty-Cycle Low-Dropout Operation
        6. 7.3.16.6 Short-Circuit Protection
        7. 7.3.16.7 Soft Start
      17. 7.3.17 Standby LDO Regulators (LDO1, LDO2)
      18. 7.3.18 Load Switches or LDO Regulators (LS1 or LDO3, LS2 or LDO4)
      19. 7.3.19 White LED Driver
    4. 7.4 Device Functional Modes
      1. 7.4.1 PMIC States
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 ACTIVE State
        3. 7.4.1.3 SLEEP State
        4. 7.4.1.4 RESET State
    5. 7.5 Programming
      1. 7.5.1 I2C Bus Operation
      2. 7.5.2 Password Protection
        1. 7.5.2.1 Level1 Protection
        2. 7.5.2.2 Level2 Protection
      3. 7.5.3 Resetting of Registers to Default Values
    6. 7.6 Register Maps
      1. 7.6.1  Register Address Map
        1. 7.6.1.1 Programming Power-Up Default Values
      2. 7.6.2  Chip ID Register (CHIPID) (Address = 0x00) [reset = 0x02]
        1. Table 2. CHIPID Register Field Descriptions
      3. 7.6.3  Power Path Control Register (PPATH) (Address = 0x01) [reset = 0x3D]
        1. Table 3. PPATH Register Field Descriptions
      4. 7.6.4  Interrupt Register (INT) (Address = 0x02) [reset = 0x80]
        1. Table 4. INT Register Field Descriptions
      5. 7.6.5  Charger Configuration Register 0 (CHGCONFIG0) (Address = 0x03) [reset = 0x00]
        1. Table 5. CHGCONFIG0 Register Field Descriptions
      6. 7.6.6  Charger Configuration Register 1 (CHGCONFIG1) (Address = 0x04) [reset = 0xB1]
        1. Table 6. CHGCONFIG1 Register Field Descriptions
      7. 7.6.7  Charger Configuration Register 2 (CHGCONFIG2) (Address = 0x05) [reset = 0x80]
        1. Table 7. CHGCONFIG2 Register Field Descriptions
      8. 7.6.8  Charger Configuration Register 3 (CHGCONFIG3) (Address = 0x06) [reset = 0xB2]
        1. Table 8. CHGCONFIG3 Register Field Descriptions
      9. 7.6.9  WLED Control Register 1 (WLEDCTRL1) (Address = 0x07) [reset = 0xB1]
        1. Table 9. WLEDCTRL1 Register Field Descriptions
      10. 7.6.10 WLED Control Register 2 (WLEDCTRL2) (Address = 0x08) [reset = 0x00]
        1. Table 10. WLEDCTRL2 Register Field Descriptions
      11. 7.6.11 MUX Control Register (MUXCTRL) (Address = 0x09) [reset = 0x00]
        1. Table 11. MUXCTRL Register Field Descriptions
      12. 7.6.12 Status Register (STATUS) (Address = 0x0A) [reset = 0x00]
        1. Table 12. STATUS Register Field Descriptions
      13. 7.6.13 Password Register (PASSWORD) (Address = 0x0B) [reset = 0x00]
        1. Table 13. Password Register (PASSWORD) Field Descriptions
      14. 7.6.14 Power Good Register (PGOOD) (Address = 0x0C) [reset = 0x00]
        1. Table 14. PGOOD Register Field Descriptions
      15. 7.6.15 Power-Good Control Register (DEFPG) (Address = 0x0D) [reset = 0x0C]
        1. Table 15. DEFPG Register Field Descriptions
      16. 7.6.16 DCDC1 Control Register (DEFDCDC1) (Address = 0x0E) [reset = 0x18]
        1. Table 16. DEFDCDC1 Register Field Descriptions
      17. 7.6.17 DCDC2 Control Register (DEFDCDC2) (Address = 0x0F) [reset = 0x08]
        1. Table 17. DEFDCDC2 Register Field Descriptions
      18. 7.6.18 DCDC3 Control Register (DEFDCDC3) (Address = 0x10) [reset = 0x08]
        1. Table 18. DEFDCDC3 Register Field Descriptions
      19. 7.6.19 Slew-Rate Control Register (DEFSLEW) (Address = 0x11) [reset = 0x06]
        1. Table 19. DEFSLEW Register Field Descriptions
      20. 7.6.20 LDO1 Control Register (DEFLDO1) (Address = 0x12) [reset = 0x09]
        1. Table 20. DEFLDO1 Register Field Descriptions
      21. 7.6.21 LDO2 Control Register (DEFLDO2) (Address = 0x13) [reset = 0x38]
        1. Table 21. DEFLDO2 Register Field Descriptions
      22. 7.6.22 Load Switch1 or LDO3 Control Register (DEFLS1) (Address = 0x14) [reset = 0x26]
        1. Table 22. DEFLS1 Register Field Descriptions
      23. 7.6.23 Load Switch2 or LDO4 Control Register (DEFLS2) (Address = 0x15) [reset = 0x3F]
        1. Table 23. DEFLS2 Register Field Descriptions
      24. 7.6.24 Enable Register (ENABLE) (Address = 0x16) [reset = 0x00]
        1. Table 24. ENABLE Register Field Descriptions
      25. 7.6.25 UVLO Control Register (DEFUVLO) (Address = 0x18) [reset = 0x00]
        1. Table 25. DEFUVLO Register Field Descriptions
      26. 7.6.26 Sequencer Register 1 (SEQ1) (Address = 0x19) [reset = 0x00]
        1. Table 26. SEQ1 Register Field Descriptions
      27. 7.6.27 Sequencer Register 2 (SEQ2) (Address = 0x1A) [reset = 0x00]
        1. Table 27. SEQ2 Register Field Descriptions
      28. 7.6.28 Sequencer Register 3 (SEQ3) (Address = 0x1B) [reset = 0x00]
        1. Table 28. SEQ3 Register Field Descriptions
      29. 7.6.29 Sequencer Register 4 (SEQ4) (Address = 0x1C) [reset = 0x40]
        1. Table 29. SEQ4 Register Field Descriptions
      30. 7.6.30 Sequencer Register 5 (SEQ5) (Address = 0x1D) [reset = 0x20]
        1. Table 30. SEQ5 Register Field Descriptions
      31. 7.6.31 Sequencer Register 6 (SEQ6) (Address = 0x1E) [reset = 0x00]
        1. Table 31. SEQ6 Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Filter Design (Inductor and Output Capacitor)
          1. 8.2.2.1.1 Inductor Selection for Buck Converters
          2. 8.2.2.1.2 Output Capacitor Selection
          3. 8.2.2.1.3 Input Capacitor Selection
        2. 8.2.2.2 5-V Operation Without a Battery
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方米6体育平台手机版_好二三四免责声明
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • RSL|48
散热焊盘机械数据 (封装 | 引脚)
订购信息

7.6.1.1 Programming Power-Up Default Values

Applying 8 V to the PWR_EN pin and writing 1b to bit 4 of register 0x2C commits the current register settings to EEPROM memory so they become the new power-up default values. Any changes made to the EEPROM-backed register settings will become permanent until bit 4 of register 0x2C is rest to 0b, which can be done manually by I2C or by power-cycling the TPS652170 device. If programming is performed in-line during production of the end equipment, PWR_EN must be returned to a voltage that meets the absolute maximum ratings before powering on the full system. When 8 V is applied at the PWR_EN pin of the TPS652170 device for programming, it will not damage the pin; however, the PWR_EN signal may contact pins of other ICs and the absolute maximum ratings of any IC other than the TPS652170 should not be violated at any time.

NOTE

Only bits marked with (E2) in the register map have EEPROM programmable power-up default settings. All other bits keep the factory settings listed in the register map. Changing the default value of unlisted bits or bits marked as reserved is not advisable and should be avoided during the programming procedure.

The EEPROM of a device can only be programmed up to 1000 times. The number of programming cycles should never exceed this amount. Contact TI for changing production settings.

NOTE

All re-programmed EEPROM settings must be validated during prototyping phase to ensure desired functionality because parts cannot be returned in case of incorrect programming. Any issues should be reported to the e2e forum.

For more detailed instructions on how to program the TPS652170 device, refer to the BOOSTXL-TPS652170 User's Guide.

Figure 29 lists the memory-mapped registers for the device registers. All register offset addresses not listed in should be considered as reserved locations and the register contents should not be modified.

Figure 29. Register Address Map
Address
(Decimal)		 Address
(Hexadecimal)		 Name Password
Protection Level		 Default
Value		 Description Section
0 0x00 CHIPID None 0x02 Chip ID Go
1 0x01 PPATH None 0x3D Power path control Go
2 0x02 INT None 0x00 Interrupt flags and masks Go
3 0x03 CHGCONFIG0 None 0x00 Charger control register 0 Go
4 0x04 CHGCONFIG1 None 0xB1 Charger control register 1 Go
5 0x05 CHGCONFIG2 None 0x80 Charger control register 2 Go
6 0x06 CHGCONFIG3 None 0xB2 Charger control register 3 Go
7 0x07 WLEDCTRL1 None 0xB1 WLED control register Go
8 0x08 WLEDCTRL2 None 0x00 WLED PWM duty cycle Go
9 0x09 MUXCTRL None 0x00 Analog multiplexer control register Go
10 0x0A STATUS None 0x00 Status register Go
11 0x0B PASSWORD None 0x00 Write password Go
12 0x0C PGOOD None 0x00 Power good (PG) flags Go
13 0x0D DEFPG Level1 0x0C Power good (PG) delay Go
14 0x0E DEFDCDC1 Level2 0x18 DCDC1 voltage adjustment Go
15 0x0F DEFDCDC2 Level2 0x08 DCDC2 voltage adjustment Go
16 0x10 DEFDCDC3 Level2 0x08 DCDC3 voltage adjustment Go
17 0x11 DEFSLEW Level2 0x06 Slew control for DCDC1, DCDC2, DCDC3, and PFM mode enable Go
18 0x12 DEFLDO1 Level2 0x09 LDO1 voltage adjustment Go
19 0x13 DEFLDO2 Level2 0x38 LDO2 voltage adjustment Go
20 0x14 DEFLS1 Level2 0x26 LS1 or LDO3 voltage adjustment Go
21 0x15 DEFLS2 Level2 0x3F LS2 or LDO4 voltage adjustment Go
22 0x16 ENABLE Level1 0x00 Enable register Go
23 0x18 DEFUVLO Level1 0x00 UVLO control register Go
24 0x19 SEQ1 Level1 0x00 Power-up STROBE definition Go
25 0x1A SEQ2 Level1 0x00 Power-up STROBE definition Go
26 0x1B SEQ3 Level1 0x00 Power-up STROBE definition Go
27 0x1C SEQ4 Level1 0x00 Power-up STROBE definition Go
28 0x1D SEQ5 Level1 0x20 Power-up delay times Go
29 0x1E SEQ6 Level1 0x00 Power-up delay times Go

Bit access types are abbreviated to fit into small table cells. Table 1 shows the abbreviation codes that are used for access types in this section.

Table 1. Access Type Codes

Access Type(1) Code Description
Read R Read-only
Read/Write R/W Read and Write
(1) Reserved bits can be R or R/W. Read-only (R) Reserved bits are not used and writing data to these bits will have no effect on device operation. Read and Write (R/W) Reserved bits are settings that cannot be modified. The reset value must always be written to these bits. Modifying a R/W Reserved bit will have an impact on device operation and can produce unwanted device behavior.
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