ZHCSKD3A November 2019 – February 2021 TPS6521815
PRODUCTION DATA
Registers 0x11 through 0x26 are protected against accidental write by a 8-bit password. The password must be written prior to writing to a protected register and automatically resets to 0x00 after the next I2C transaction, regardless of the register accessed or transaction type (read or write). The password is required for write access only and is not required for read access.
To write to a protected register:
The cycle must be repeated for any other register that is Level1 write protected.
The FSEAL (freshness seal) bit prevents accidental shut-down of the always-on supplies, DCDC5 and DCDC6. The FSEAL bit exists in a default state of 0b, and can be set to 1b and reset to 0b once for factory testing. The second time the bit is set to 1b, it remains 1b and cannot reset again under software control. Coin-cell battery and main supply must be disconnected from the device to reset the FSEAL bit again. With the FSEAL bit set to 1b, DCDC5 and DCDC6 are forced ON regardless of the state of the DC5_EN and DC6_EN bit, and the rails do not turn off when the device enters the OFF state.
A consecutive write of [0xB1, 0xFE, and 0xA3] to the password register sets the FSEAL bit to 1b. The three bytes must be written consecutively for the sequence to be valid. No other read or write transactions are allowed between the three bytes, or the sequence is invalid. After a valid sequence, the FSEAL bit in the STATUS register reflects the new setting.
After setting the FSEAL bit, the device can enter the OFF state or any other mode of operation without affecting the state of the FSEAL bit, provided the coin-cell supply remains connected to the chip.
A second write of [0xB1, 0xFE, and 0xA3] to the password register resets the FSEAL bit to 0b. The three bytes must be written consecutively for the sequence to be valid.
A third write of [0xB1, 0xFE, and 0xA3] to the password register sets the FSEAL bit to 1b and locks it into this state for as long as the coin-cell supply (CC) remains connected to the device.
The FLAG register contains a bit for each power rail and GPO to keep track of the enable state of the rails while the system is suspended. The following rules apply to the FLAG register:
The host processor reads the FLAG register to determine if the system powered up from the OFF or SUSPEND state. In the SUSPEND state, typically the DDR memory is kept in self refresh mode and therefore the DC3_FLG or DC4_FLG bits are set.
#TPS65218_TABLE lists the memory-mapped registers for the TPS6521815. All register offset addresses not listed in #TPS65218_TABLE should be considered as reserved locations and the register contents should not be modified.
| SUBADDRESS | ACRONYM | REGISTER NAME | R/W | PASSWORD PROTECTED | SECTION |
|---|---|---|---|---|---|
| 0x00 | CHIPID | CHIP ID | R | No | Go |
| 0x01 | INT1 | INTERRUPT 1 | R | No | Go |
| 0x02 | INT2 | INTERRUPT 2 | R | No | Go |
| 0x03 | INT_MASK1 | INTERRUPT MASK 1 | R/W | No | Go |
| 0x04 | INT_MASK2 | INTERRUPT MASK 2 | R/W | No | Go |
| 0x05 | STATUS | STATUS | R | No | Go |
| 0x06 | CONTROL | CONTROL | R/W | No | Go |
| 0x07 | FLAG | FLAG | R | No | Go |
| 0x10 | PASSWORD | PASSWORD | R/W | No | Go |
| 0x11 | ENABLE1 | ENABLE 1 | R/W | Yes | Go |
| 0x12 | ENABLE2 | ENABLE 2 | R/W | Yes | Go |
| 0x13 | CONFIG1 | CONFIGURATION 1 | R/W | Yes | Go |
| 0x14 | CONFIG2 | CONFIGURATION 2 | R/W | Yes | Go |
| 0x15 | CONFIG3 | CONFIGURATION 3 | R/W | Yes | Go |
| 0x16 | DCDC1 | DCDC1 CONTROL | R/W | Yes | Go |
| 0x17 | DCDC2 | DCDC2 CONTROL | R/W | Yes | Go |
| 0x18 | DCDC3 | DCDC3 CONTROL | R/W | Yes | Go |
| 0x19 | DCDC4 | DCDC4 CONTROL | R/W | Yes | Go |
| 0x1A | SLEW | SLEW RATE CONTROL | R/W | Yes | Go |
| 0x1B | LDO1 | LDO1 CONTROL | R/W | Yes | Go |
| 0x20 | SEQ1 | SEQUENCER 1 | R/W | Yes | Go |
| 0x21 | SEQ2 | SEQUENCER 2 | R/W | Yes | Go |
| 0x22 | SEQ3 | SEQUENCER 3 | R/W | Yes | Go |
| 0x23 | SEQ4 | SEQUENCER 4 | R/W | Yes | Go |
| 0x24 | SEQ5 | SEQUENCER 5 | R/W | Yes | Go |
| 0x25 | SEQ6 | SEQUENCER 6 | R/W | Yes | Go |
| 0x26 | SEQ7 | SEQUENCER 7 | R/W | Yes | Go |
#REGISTER_LEGEND_1 explains the common abbreviations used in this section.
| Abbreviation | Description |
|---|---|
| R | Read |
| W | Write |
| R/W | Read and write capable |
| E2 | Backed by EEPROM |
| h | Hexadecimal notation of a group of bits |
| b | Hexadecimal notation of a bit or group of bits |
| X | Do not care reset value |
CHIPID is shown in #TPS65218_CHIPID_FIGURE and described in #TPS65218_CHIPID_TABLE.
Return to Summary Table.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| CHIP | REV | ||||||
| R-2h | R-5h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-3 | CHIP | R | 2h |
Chip ID: 0h = TPS65218D0 1h = Future use 2h = TPS6521815 3h = Future use 4h = TPS6521825 5h = Future use
... 1Fh = Future use |
| 2-0 | REV | R | 5h |
Revision code: 0h = Revision 1.0 1h = Revision 1.1 2h = Revision 2.0 3h = Revision 2.1 4h = Revision 3.0 5h = Revision 4.0 (D0) 6h = Future use 7h = Future use |
INT1 is shown in #TPS65218_INT1_FIGURE and described in #TPS65218_INT1_TABLE.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VPRG | AC | PB | HOT | CC_AQC | PRGC | |
| R-00b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 00b | |
| 5 | VPRG | R | 0b |
Programming voltage interrupt: 0b = No significance. 1b = Input voltage is too low for programming power-up default values. |
| 4 | AC | R | 0b |
AC_DET pin status change interrupt. Note: Status information is available in STATUS register. 0b = No change in status. 1b = AC_DET status change (AC_DET pin changed high to low or low to high). |
| 3 | PB | R | 0b |
Push-button status change interrupt. Note: Status information is available in STATUS register 0b = No change in status. 1b = Push-button status change (PB changed high to low or low to high). |
| 2 | HOT | R | 0b |
Thermal shutdown early warning: 0b = Chip temperature is below HOT threshold. 1b = Chip temperature exceeds HOT threshold. |
| 1 | CC_AQC | R | 0b |
Coin cell battery voltage acquisition complete interrupt: 0b = No significance. 1b = Backup battery status comparators have settled and results are available in STATUS register. |
| 0 | PRGC | R | 0b |
EEPROM programming complete interrupt: 0b = No significance. 1b = Programming of power-up default settings has completed successfully. |
INT2 is shown in #TPS65218_INT2_FIGURE and described in #TPS65218_INT2_TABLE.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LS3_F | LS2_F | LS1_F | LS3_I | LS2_I | LS1_I | |
| R-00b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 00b | |
| 5 | LS3_F | R | 0b |
Load switch 3 fault interrupt: 0b = No fault. Switch is working normally. 1b = Load switch exceeded operating temperature limit and is temporarily disabled. |
| 4 | LS2_F | R | 0b |
Load switch 2 fault interrupt: 0b = No fault. Switch is working normally. 1b = Load switch exceeded operating temperature limit or input voltage dropped below minimum value. Switch is temporarily disabled. |
| 3 | LS1_F | R | 0b |
Load switch 1 fault interrupt: 0b = No fault. Switch is working normally. 1b = Load switch exceeded operating temperature limit and is temporarily disabled. |
| 2 | LS3_I | R | 0b |
Load switch 3 current-limit interrupt: 0b = Load switch is disabled or not in current limit. 1b = Load switch is actively limiting the output current (output load is exceeding current limit value). |
| 1 | LS2_I | R | 0b |
Load switch 2 current-limit interrupt: 0b = Load switch is disabled or not in current limit. 1b = Load switch is actively limiting the output current (output load is exceeding current limit value). |
| 0 | LS1_I | R | 0b |
Load switch 1 current-limit interrupt: 0b = Load switch is disabled or not in current limit. 1b = Load switch is actively limiting the output current (output load is exceeding current limit value). |
INT_MASK1 is shown in #TPS65218_INT_MASK1_FIGURE and described in #TPS65218_INT_MASK1_TABLE.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | VPRGM | ACM | PBM | HOTM | CC_AQCM | PRGCM | |
| R-00b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 00b | |
| 5 | VPRGM | R/W | 0b |
Programming voltage interrupt mask bit. Note: mask bit has no effect on monitoring function: 0b = Interrupt is unmasked (interrupt event pulls nINT pin low). 1b = Interrupt is masked (interrupt has no effect on nINT pin). |
| 4 | ACM | R/W | 0b |
AC_DET interrupt masking bit: 0b = Interrupt is unmasked (interrupt event pulls nINT pin low). 1b = Interrupt is masked (interrupt has no effect on nINT pin). Note: mask bit has no effect on monitoring function. |
| 3 | PBM | R/W | 0b |
PB interrupt masking bit. Note: mask bit has no effect on monitoring function. 0b = Interrupt is unmasked (interrupt event pulls nINT pin low). 1b = Interrupt is masked (interrupt has no effect on nINT pin). |
| 2 | HOTM | R/W | 0b |
HOT interrupt masking bit. Note: mask bit has no effect on monitoring function. 0b = Interrupt is unmasked (interrupt event pulls nINT pin low). 1b = Interrupt is masked (interrupt has no effect on nINT pin). |
| 1 | CC_AQCM | R/W | 0b |
C_AQC interrupt masking bit. Note: mask bit has no effect on monitoring function. 0b = Interrupt is unmasked (interrupt event pulls nINT pin low). 1b = Interrupt is masked (interrupt has no effect on nINT pin). |
| 0 | PRGCM | R/W | 0b |
PRGC interrupt masking bit. Note: mask bit has no effect on monitoring function. 0b = Interrupt is unmasked (interrupt event pulls nINT pin low). 1b = Interrupt is masked (interrupt has no effect on nINT pin). |
INT_MASK2 is shown in #TPS65218_INT_MASK2_FIGURE and described in #TPS65218_INT_MASK2_TABLE.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LS3_FM | LS2_FM | LS1_FM | LS3_IM | LS2_IM | LS1_IM | |
| R-00b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 00b | |
| 5 | LS3_FM | R/W | 0b |
LS3 fault interrupt mask bit. Note: mask bit has no effect on monitoring function. 0b = Interrupt is unmasked (interrupt event pulls nINT pin low). 1b = Interrupt is masked (interrupt has no effect on nINT pin). |
| 4 | LS2_FM | R/W | 0b |
LS2 fault interrupt mask bit. Note: mask bit has no effect on monitoring function. 0b = Interrupt is unmasked (interrupt event pulls nINT pin low). 1b = Interrupt is masked (interrupt has no effect on nINT pin). |
| 3 | LS1_FM | R/W | 0b |
LS1 fault interrupt mask bit. Note: mask bit has no effect on monitoring function. 0b = Interrupt is unmasked (interrupt event pulls nINT pin low). 1b = Interrupt is masked (interrupt has no effect on nINT pin). |
| 2 | LS3_IM | R/W | 0b |
LS3 current-limit interrupt mask bit. Note: mask bit has no effect on monitoring function. 0b = Interrupt is unmasked (interrupt event pulls nINT pin low). 1b = Interrupt is masked (interrupt has no effect on nINT pin). |
| 1 | LS2_IM | R/W | 0b |
LS2 current-limit interrupt mask bit. Note: mask bit has no effect on monitoring function. 0b = Interrupt is unmasked (interrupt event pulls nINT pin low). 1b = Interrupt is masked (interrupt has no effect on nINT pin). |
| 0 | LS1_IM | R/W | 0b |
LS1 current-limit interrupt mask bit. Note: mask bit has no effect on monitoring function. 0b = Interrupt is unmasked (interrupt event pulls nINT pin low). 1b = Interrupt is masked (interrupt has no effect on nINT pin). |
Register mask: C0h
STATUS is shown in #TPS65218_STATUS_FIGURE and is described in #TPS65218_STATUS_TABLE.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| FSEAL | EE | AC_STATE | PB_STATE | STATE | CC_STAT | ||
| R-0b | R-0b | R-X | R-X | R-X | R-X | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | FSEAL | R | 0b |
Freshness seal (FSEAL) status. Note: See #SLDS2066086 for details. 0b = FSEAL is in native state (fresh). 1b = FSEAL is broken. |
| 6 | EE | R | 0b |
EEPROM status: 0b = EEPROM values have not been changed from factory default setting. 1b = EEPROM values have been changed from factory default settings. |
| 5 | AC_STATE | R | X |
AC_DET input status bit: 0b = AC_DET input is inactive (AC_DET input pin is high). 1b = AC_DET input is active (AC_DET input is low). |
| 4 | PB_STATE | R | X |
PB input status bit: 0b = Push Button input is inactive (PB input pin is high). 1b = Push Button input is active (PB input pin is low). |
| 3-2 | STATE | R | X |
State machine STATE indication: 0h = PMIC is in transitional state. 1h = PMIC is in WAIT_PWR_EN state. 2h = PMIC is in ACTIVE state. 3h = PMIC is in SUSPEND state. |
| 1-0 | CC_STAT | R | X |
Coin cell state of charge. Note: Coin-cell voltage acquisition must be triggered first before status bits are valid. See CC_AQ bit in #TPS65218_CONTROL. 0h = VCC < VLOW_LEVEL; Coin cell is not present or approaching end-of-life (EOL). 1h = VLOW_LEVEL < VCC < VGOOD_LEVEL; Coin cell voltage is LOW. 2h = VGOOD_LEVEL < VCC <VIDEAL_LEVEL; Coin cell voltage is GOOD. 3h = VIDEAL < VCC; Coin cell voltage is IDEAL. |
CONTROL is shown in #TPS65218_CONTROL_FIGURE and described in #TPS65218_CONTROL_TABLE.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | OFFnPFO | CC_AQ | |||||
| R-0000 00b | R/W-0b | R/W-0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-2 | RESERVED | R | 0000 00b | |
| 1 | OFFnPFO | R/W | 0b |
Power-fail shutdown bit: 0b = nPFO has no effect on PMIC state. 1b = All rails are shut down and PMIC enters OFF state when PFI comparator trips (nPFO is low). |
| 0 | CC_AQ | R/W | 0b |
Coin Cell battery voltage acquisition start bit: 0b = No significance 1b = Triggers voltage acquisition. Bit is automatically reset to 0. |
FLAG is shown in #TPS65218_FLAG_FIGURE and described in #TPS65218_FLAG_TABLE.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPO3_FLG | GPO2_FLG | GPO1_FLG | LDO1_FLG | DC4_FLG | DC3_FLG | DC2_FLG | DC1_FLG |
| R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b | R-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GPO3_FLG | R | 0b |
GPO3 Flag bit: 0b = Device powered up from OFF or SUSPEND state and GPO3 was disabled while in SUSPEND. 1b = Device powered up from SUSPEND state and GPO3 was enabled while in SUSPEND. |
| 6 | GPO2_FLG | R | 0b |
GPO2 Flag bit 0b = Device powered up from OFF or SUSPEND state and GPO2 was disabled while in SUSPEND. 1b = Device powered up from SUSPEND state and GPO2 was enabled while in SUSPEND. |
| 5 | GPO1_FLG | R | 0b |
GPO1 Flag bit: 0b = Device powered up from OFF or SUSPEND state and GPO1 was disabled while in SUSPEND. 1b = Device powered up from SUSPEND state and GPO1 was enabled while in SUSPEND. |
| 4 | LDO1_FLG | R | 0b |
LDO1 Flag bit: 0b = Device powered up from OFF or SUSPEND state and LDO1 was disabled while in SUSPEND. 1b = Device powered up from SUSPEND state and LDO1 was enabled while in SUSPEND. |
| 3 | DC4_FLG | R | 0b |
DCDC4 Flag bit: 0b = Device powered up from OFF or SUSPEND state and DCDC4 was disabled while in SUSPEND. 1b = Device powered up from SUSPEND state and DCDC4 was enabled while in SUSPEND. |
| 2 | DC3_FLG | R | 0b |
DCDC3 Flag bit: 0b = Device powered up from OFF or SUSPEND state and DCDC3 was disabled while in SUSPEND. 1b = Device powered up from SUSPEND state and DCDC3 was enabled while in SUSPEND. |
| 1 | DC2_FLG | R | 0b |
DCDC2 Flag bit: 0b = Device powered up from OFF or SUSPEND state and DCDC2 was disabled while in SUSPEND. 1b = Device powered up from SUSPEND state and DCDC2 was enabled while in SUSPEND. |
| 0 | DC1_FLG | R | 0b |
DCDC1 Flag bit: 0b = Device powered up from OFF or SUSPEND state and DCDC1 was disabled while in SUSPEND. 1b = Device powered up from SUSPEND state and GDCDC1PO3 was enabled while in SUSPEND. |
PASSWORD is shown in #TPS65218_PASSWORD_FIGURE and described in #TPS65218_PASSWORD_TABLE.
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| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PWRD | |||||||
| R/W-00h | |||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-0 | PWRD | R/W | 00h |
Register is used for accessing password protected registers (see #SLDS2066425 for details). Breaking the freshness seal (see #SLDS2066086 for details). Programming power-up default values (see GUID-870AF153-4842-4EFD-901F-B71E1E4D1888.html for details). Read-back always yields 0x00. |
ENABLE1 is shown in #TPS65218_ENABLE1_FIGURE and described in #TPS65218_ENABLE1_TABLE.
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Password protected.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DC6_EN | DC5_EN | DC4_EN | DC3_EN | DC2_EN | DC1_EN | |
| R-00b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 00b | |
| 5 | DC6_EN | R/W | 0b |
DCDC6 enable bit. DCDC6 can only be disabled if FSEAL = 0. See #SLDS2066086 for details. 0b = Disabled 1b = Enabled |
| 4 | DC5_EN | R/W | 0b |
DCDC5 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer. DCDC5 can only be disabled if FSEAL = 0. See #SLDS2066086 for details. 0b = Disabled 1b = Enabled |
| 3 | DC4_EN | R/W | 0b |
DCDC4 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer. 0b = Disabled 1b = Enabled |
| 2 | DC3_EN | R/W | 0b |
DCDC3 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer. 0b = Disabled 1b = Enabled |
| 1 | DC2_EN | R/W | 0b |
DCDC2 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer. 0b = Disabled 1b = Enabled |
| 0 | DC1_EN | R/W | 0b |
DCDC1 enable bit. Note: At power-up and down this bit is automatically updated by the internal power sequencer. 0b = Disabled 1b = Enabled |
ENABLE2 is shown in #TPS65218_ENABLE2_FIGURE and described in #TPS65218_ENABLE2_TABLE.
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Password protected.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | GPIO3 | GPIO2 | GPIO1 | LS3_EN | LS2_EN | LS1_EN | LDO1_EN |
| R-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RESERVED | R | 0b | |
| 6 | GPIO3 | R/W | 0b |
General purpose output 3 / reset polarity. Note: If DC12_RST bit (register 0x14) is set to 1 this bit has no function. 0b = GPIO3 output is driven low. 1b = GPIO3 output is HiZ. |
| 5 | GPIO2 | R/W | 0b |
General purpose output 2. Note: If IO_SEL bit (register 0x13) is set to 1 this bit has no function. 0b = GPO2 output is driven low. 1b = GPO2 output is HiZ. |
| 4 | GPIO1 | R/W | 0b |
General purpose output 1. Note: If IO_SEL bit (register 0x13) is set to 1 this bit has no function. 0b = GPO1 output is driven low. 1b = GPO1 output is HiZ. |
| 3 | LS3_EN | R/W | 0b |
Load switch 3 (LS3) enable bit. 0b = Disabled 1b = Enabled |
| 2 | LS2_EN | R/W | 0b |
Load switch 2 (LS2) enable bit. 0b = Disabled 1b = Enabled |
| 1 | LS1_EN | R/W | 0b |
Load switch 1 (LS1) enable bit. 0b = Disabled 1b = Enabled Note: At power-up and down this bit is automatically updated by the internal power sequencer. |
| 0 | LDO1_EN | R/W | 0b |
LDO1 enable bit. 0b = Disabled 1b = Enabled Note: At power-up and down this bit is automatically updated by the internal power sequencer. |
CONFIG1 is shown in #TPS65218_CONFIG1_FIGURE and described in #TPS65218_CONFIG1_TABLE.
Return to Summary Table.
Password protected.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| TRST | GPO2_BUF | IO1_SEL | PGDLY | STRICT | UVLO | ||
| R/W-0b | R/W-0b | R/W-0b | R/W-01b | R/W-0b | R/W-00b | ||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | TRST | R/W, E2 | 0b |
Push-button reset time constant: 0b = 8 s 1b = 15 s |
| 6 | GPO2_BUF | R/W, E2 | 0b |
GPO2 output buffer configuration: 0b = GPO2 buffer is configured as open-drain. 1b = GPO2 buffer is configured as push-pull (high-level is driven to IN_LS1). |
| 5 | IO1_SEL | R/W, E2 | 0b |
GPIO1 / GPO2 configuration bit. See GUID-95DCE928-CFE8-4BC5-8DFF-BE7F13DCFD84.html#GUID-95DCE928-CFE8-4BC5-8DFF-BE7F13DCFD84 for details. 0b = GPIO1 is configured as general-purpose, open-drain output. GPO2 is independent output. 1b = GPIO1 is configured as input, controlling GPO2. Intended for DDR3 reset signal control. |
| 4-3 | PGDLY | R/W, E2 | 01b |
Power-Good delay. Note: Power-good delay applies to rising-edge only (power-up), not falling edge (power-down or fault). 00b = 10 ms 01b = 20 ms 10b = 50 ms 11b = 150 ms |
| 2 | STRICT | R/W, E2 | 0b |
Supply Voltage Supervisor Sensitivity selection. See GUID-7E74B44F-7C67-473D-A877-6F22434F1BCC.html#GUID-7E74B44F-7C67-473D-A877-6F22434F1BCC for details. 0b = Power-good threshold (VOUT falling) has wider limits. Over-voltage is not monitored. 1b = Power-good threshold (VOUT falling) has tight limits. Over-voltage is monitored. |
| 1-0 | UVLO | R/W, E2 | 00b |
UVLO setting 00b = 2.75 V 01b = 2.95 V 10b = 3.25 V 11b = 3.35 V |
CONFIG2 is shown in #TPS65218_CONFIG2_FIGURE and described in #TPS65218_CONFIG2_TABLE.
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Password protected.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DC12_RST | UVLOHYS | RESERVED | LS3ILIM | LS2ILIM | |||
| R/W- 0b | R/W-1b | R-00b | R/W-00b | R/W-00b | |||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | DC12_RST | R/W, E2 | 0b |
DCDC1 and DCDC2 reset-pin enable: 0b = GPIO3 is configured as general-purpose output. 1b = GPIO3 is configured as warm-reset input to DCDC1 and DCDC2. |
| 6 | UVLOHYS | R/W, E2 | 1b |
UVLO hysteresis: 0b = 200 mV 1b = 400 mV |
| 5-4 | RESERVED | R | 00b | |
| 3-2 | LS3ILIM | R/W | 00b |
Load switch 3 (LS3) current limit selection: 00b = 100 mA, (MIN = 98 mA) 01b = 200 mA, (MIN = 194 mA) 10b = 500 mA, (MIN = 475 mA) 11b = 1000 mA, (MIN = 900 mA) See the LS3 current limit specification in GUID-7E74B44F-7C67-473D-A877-6F22434F1BCC.html#GUID-7E74B44F-7C67-473D-A877-6F22434F1BCC for more details. |
| 1-0 | LS2ILIM | R/W | 00b |
Load switch 2 (LS2) current limit selection: 00b = 100 mA, (MIN = 94 mA) 01b = 200 mA, (MIN = 188 mA) 10b = 500 mA, (MIN = 465 mA) 11b = 1000 mA, (MIN = 922 mA) See the LS2 current limit specification in GUID-7E74B44F-7C67-473D-A877-6F22434F1BCC.html#GUID-7E74B44F-7C67-473D-A877-6F22434F1BCC for more details. |
CONFIG3 is shown in #TPS65218_CONFIG3_FIGURE and described in #TPS65218_CONFIG3_TABLE.
Return to Summary Table.
Password protected.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LS3nPFO | LS2nPFO | LS1nPFO | LS3DCHRG | LS2DCHRG | LS1DCHRG | |
| R-00b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 00b | |
| 5 | LS3nPFO | R/W | 0b |
Load switch 3 power-fail disable bit: 0b = Load switch status is not affected by power-fail comparator. 1b = Load switch is disabled if power-fail comparator trips (nPFO is low). |
| 4 | LS2nPFO | R/W | 0b |
Load switch 2 power-fail disable bit: 0b = Load switch status is not affected by power-fail comparator. 1b = Load switch is disabled if power-fail comparator trips (nPFO is low). |
| 3 | LS1nPFO | R/W | 0b |
Load switch 1 power-fail disable bit: 0b = Load switch status is not affected by power-fail comparator. 1b = Load switch is disabled if power-fail comparator trips (nPFO is low). |
| 2 | LS3DCHRG | R/W | 0b |
Load switch 3 discharge enable bit: 0b = Active discharge is disabled. 1b = Active discharge is enabled (load switch output is actively discharged when switch is OFF). |
| 1 | LS2DCHRG | R/W | 0b |
Load switch 2 discharge enable bit: 0b = Active discharge is disabled. 1b = Active discharge is enabled (load switch output is actively discharged when switch is OFF). |
| 0 | LS1DCHRG | R/W | 0b |
Load switch 1 discharge enable bit: 0b = Active discharge is disabled. 1b = Active discharge is enabled (load switch output is actively discharged when switch is OFF). |
DCDC1 is shown in #TPS65218_DCDC1_FIGURE and described in #TPS65218_DCDC1_TABLE.
Return to Summary Table.
Note 1: This
register is password protected. For more information, see #SLDS2066425.
Note 2: A 5-ms blanking time of the over-voltage and
under-voltage monitoring occurs when a write is performed on the DCDC1 register.
Note 3: To change the output voltage of DCDC1, the GO bit or
the GODSBL bit must be set to 1b in register 0x1A.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PFM | RESERVED | DCDC1 | |||||
| R/W-1b | R-0b | R/W-00h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | PFM | R/W | 1b |
Pulse Frequency Modulation (PFM, also known as pulse-skip-mode) enable. PFM mode improves light-load efficiency. Actual PFM mode operation depends on load condition. 0b = Disabled (forced PWM) 1b = Enabled |
| 6 | RESERVED | R | 0b | |
| 5-0 | DCDC1 | R/W, E2 | 00h |
DCDC1 output voltage setting: 0h = 0.850 1h = 0.860 2h = 0.870 3h = 0.880 4h = 0.890 5h = 0.900 6h = 0.910 7h = 0.920 8h = 0.930 9h = 0.940 Ah = 0.950 Bh = 0.960 Ch = 0.970 Dh = 0.980 Eh = 0.990 Fh = 1.000 10h = 1.010 11h = 1.020 12h = 1.030 13h = 1.040 14h = 1.050 15h = 1.060 16h = 1.070 17h = 1.080 18h = 1.090 19h = 1.100 1Ah = 1.110 1Bh = 1.120 1Ch = 1.130 1Dh = 1.140 1Eh = 1.150 1Fh = 1.160 20h = 1.170 21h = 1.180 22h = 1.190 23h = 1.200 |
|
24h = 1.210 25h = 1.220 26h = 1.230 27h = 1.240 28h = 1.250 29h = 1.260 2Ah = 1.270 2Bh = 1.280 2Ch = 1.290 2Dh = 1.300 2Eh = 1.310 2Fh = 1.320 30h = 1.330 31h = 1.340 32h = 1.350 33h = 1.375 34h = 1.400 35h = 1.425 36h = 1.450 37h = 1.475 38h = 1.500 39h = 1.525 3Ah = 1.550 3Bh = 1.575 3Ch = 1.600 3Dh = 1.625 3Eh = 1.650 3Fh = 1.675 |
DCDC2 is shown in #TPS65218_DCDC2_FIGURE and described in #TPS65218_DCDC2_TABLE.
Return to Summary Table.
Note 1: This register is password protected. For more information,
see #SLDS2066425.
Note 2: A 5-ms blanking
time of the over-voltage and under-voltage monitoring occurs when a
write is performed on the DCDC2 register.
Note 3: To change the output
voltage of DCDC2, the GO bit or the GODSBL bit must be set to 1b in
register 0x1A.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PFM | RESERVED | DCDC2 | |||||
| R/W-1b | R-0b | R/W-00h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | PFM | R/W | 1b |
Pulse frequency modulation (PFM, also known as pulse-skip-mode) enable. PFM mode improves light-load efficiency. Actual PFM mode operation depends on load condition. 0b = Disabled (forced PWM) 1b = Enabled |
| 6 | RESERVED | R | 0b | |
| 5-0 | DCDC2 | R/W, E2 | 00h |
DCDC2 output voltage setting: 0h = 0.850 1h = 0.860 2h = 0.870 3h = 0.880 4h = 0.890 5h = 0.900 6h = 0.910 7h = 0.920 8h = 0.930 9h = 0.940 Ah = 0.950 Bh = 0.960 Ch = 0.970 Dh = 0.980 Eh = 0.990 Fh = 1.000 10h = 1.010 11h = 1.020 12h = 1.030 13h = 1.040 14h = 1.050 15h = 1.060 16h = 1.070 17h = 1.080 18h = 1.090 19h = 1.100 1Ah = 1.110 1Bh = 1.120 1Ch = 1.130 1Dh = 1.140 1Eh = 1.150 1Fh = 1.160 20h = 1.170 21h = 1.180 22h = 1.190 23h = 1.200 |
|
24h = 1.210 25h = 1.220 26h = 1.230 27h = 1.240 28h = 1.250 29h = 1.260 2Ah = 1.270 2Bh = 1.280 2Ch = 1.290 2Dh = 1.300 2Eh = 1.310 2Fh = 1.320 30h = 1.330 31h = 1.340 32h = 1.350 33h = 1.375 34h = 1.400 35h = 1.425 36h = 1.450 37h = 1.475 38h = 1.500 39h = 1.525 3Ah = 1.550 3Bh = 1.575 3Ch = 1.600 3Dh = 1.625 3Eh = 1.650 3Fh = 1.675 |
DCDC3 is shown in #TPS65218_DCDC3_FIGURE and described in #TPS65218_DCDC3_TABLE.
Return to Summary Table.
Note 1: This register is password protected. For more information,
see #SLDS2066425.
Note 2: A 5-ms blanking
time of the over-voltage and under-voltage monitoring occurs when a
write is performed on the DCDC3 register.
Power-up default may differ depending on RSEL value. See GUID-0ACB1843-781C-43C2-A01A-911960C64E9A.html#GUID-0ACB1843-781C-43C2-A01A-911960C64E9A for details.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PFM | RESERVED | DCDC3 | |||||
| R/W-1b | R-0b | R/W-00h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | PFM | R/W | 1b |
Pulse Frequency Modulation (PFM, also known as pulse-skip-mode) enable. PFM mode improves light-load efficiency. Actual PFM mode operation depends on load condition. 0b = Disabled (forced PWM) 1b = Enabled |
| 6 | RESERVED | R | 0b | |
| 5-0 | DCDC3 | R/W, E2 | 00h |
DCDC3 output voltage setting: 0h = 0.900 1h = 0.925 2h = 0.950 3h = 0.975 4h = 1.000 5h = 1.025 6h = 1.050 7h = 1.075 8h = 1.100 9h = 1.125 Ah = 1.150 Bh = 1.175 Ch = 1.200 Dh = 1.225 Eh = 1.250 Fh = 1.275 10h = 1.300 11h = 1.325 12h = 1.350 13h = 1.375 14h = 1.400 15h = 1.425 16h = 1.450 17h = 1.475 18h = 1.500 19h = 1.525 1Ah = 1.550 1Bh = 1.600 1Ch = 1.650 1Dh = 1.700 1Eh = 1.750 1Fh = 1.800 20h = 1.850 21h = 1.900 22h = 1.950 23h = 2.000 |
|
24h = 2.050 25h = 2.100 26h = 2.150 27h = 2.200 28h = 2.250 29h = 2.300 2Ah = 2.350 2Bh = 2.400 2Ch = 2.450 2Dh = 2.500 2Eh = 2.550 2Fh = 2.600 30h = 2.650 31h = 2.700 32h = 2.750 33h = 2.800 34h = 2.850 35h = 2.900 36h = 2.950 37h = 3.000 38h = 3.050 39h = 3.100 3Ah = 3.150 3Bh = 3.200 3Ch = 3.250 3Dh = 3.300 3Eh = 3.350 3Fh = 3.400 |
DCDC4 is shown in #TPS65218_DCDC4_FIGURE and described in #TPS65218_DCDC4_TABLE.
Return to Summary Table.
Note 1: This register is password protected. For more information,
see #SLDS2066425.
Note 2: A 5-ms blanking
time of the over-voltage and under-voltage monitoring occurs when a
write is performed on the DCDC4 register.
Power-up default may differ depending on RSEL value. See GUID-0ACB1843-781C-43C2-A01A-911960C64E9A.html#GUID-0ACB1843-781C-43C2-A01A-911960C64E9A for details. The Reserved setting should not be selected and the output voltage settings should not be modified while the converter is operating.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| PFM | RESERVED | DCDC4 | |||||
| R/W-1b | R-0b | R/W-00h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | PFM | R/W | 1b |
Pulse Frequency Modulation (PFM, also known as pulse-skip-mode) enable. PFM mode improves light-load efficiency. Actual PFM mode operation depends on load condition. 0b = Disabled (forced PWM) 1b = Enabled |
| 6 | RESERVED | R | 0b | |
| 5-0 | DCDC4 | R/W, E2 | 00h |
DCDC4 output voltage setting: 0h = 1.175 1h = 1.200 2h = 1.225 3h = 1.250 4h = 1.275 5h = 1.300 6h = 1.325 7h = 1.350 8h = 1.375 9h = 1.400 Ah = 1.425 Bh = 1.450 Ch = 1.475 Dh = 1.500 Eh = 1.525 Fh = 1.550 10h = 1.600 11h = 1.650 12h = 1.700 13h = 1.750 14h = 1.800 15h = 1.850 16h = 1.900 17h = 1.950 18h = 2.000 19h = 2.050 1Ah = 2.100 1Bh = 2.150 1Ch = 2.200 1Dh = 2.250 1Eh = 2.300 1Fh = 2.3500 20h = 2.400 21h = 2.450 22h = 2.500 23h = 2.550 |
|
24h = 2.600 25h = 2.650 26h = 2.700 27h = 2.750 28h = 2.800 29h = 2.850 2Ah = 2.900 2Bh = 2.950 2Ch = 3.000 2Dh = 3.050 2Eh = 3.100 2Fh = 3.150 30h = 3.200 31h = 3.250 32h = 3.300 33h = 3.350 34h = 3.400 35h = reserved 36h = reserved 37h = reserved 38h = reserved 39h = reserved 3Ah = reserved 3Bh = reserved 3Ch = reserved 3Dh = reserved 3Eh = reserved 3Fh = reserved |
SLEW is shown in #TPS65218_SLEW_FIGURE and described in #TPS65218_SLEW_TABLE.
Return to Summary Table.
Slew-rate control applies to DCDC1 and DCDC2 only. If changing from a higher voltage to lower voltage while STRICT = 1 and converters are in a no load state, PFM bit for DCDC1 and DCDC2 must be set to 0.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GO | GODSBL | RESERVED | SLEW | ||||
| R/W-0b | R/W-0b | R-000b | R/W-6h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | GO | R/W | 0b |
Go bit. Note: Bit is automatically reset at the end of the voltage transition. 0b = No change 1b = Initiates the transition from present state to the output voltage setting currently stored in DCDC1 and DCDC2 register. SLEW setting does apply. |
| 6 | GODSBL | R/W | 0b |
Go disable bit 0b = Enabled 1b = Disabled; DCDC1 and DCDC2 output voltage changes whenever set-point is updated in DCDC1 and DCDC2 register without having to write to the GO bit. SLEW setting does apply. |
| 5-3 | RESERVED | R | 000b | |
| 2-0 | SLEW | R/W | 6h |
Output slew rate setting: 0h = 160 µs/step (0.0625 mV/µs at 10 mV per step) 1h = 80 µs/step (0.125 mV/µs at 10 mV per step) 2h = 40 µs/step (0.250 mV/µs at 10 mV per step) 3h = 20 µs/step (0.500 mV/µs at 10 mV per step) 4h = 10 µs/step (1.0 mV/µs at 10 mV per step) 5h = 5 µs/step (2.0 mV/µs at 10 mV per step) 6h = 2.5 µs/step (4.0 mV/µs at 10 mV per step) 7h = Immediate; slew rate is only limited by control loop response time. Note: The actual slew rate depends on the voltage step per code. Refer to DCDCx registers for details. |
LDO1 is shown in #TPS65218_LDO1_FIGURE and described in #TPS65218_LDO1_TABLE.
Return to Summary Table.
Note 1: This register is password protected. For more information,
see #SLDS2066425.
Note 2: A 5-ms blanking
time of the over-voltage and under-voltage monitoring occurs when a
write is performed on the LDO1 register.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | LDO1 | ||||||
| R-00b | R/W-1Fh | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 00b | |
| 5-0 | LDO1 | R/W, E2 | 1Fh |
LDO1 output voltage setting: 0h = 0.900 1h = 0.925 2h = 0.950 3h = 0.975 4h = 1.000 5h = 1.025 6h = 1.050 7h = 1.075 8h = 1.100 9h = 1.125 Ah = 1.150 Bh = 1.175 Ch = 1.200 Dh = 1.225 Eh = 1.250 Fh = 1.275 10h = 1.300 11h = 1.325 12h = 1.350 13h = 1.375 14h = 1.400 15h = 1.425 16h = 1.450 17h = 1.475 18h = 1.500 19h = 1.525 |
|
1Ah = 1.550 1Bh = 1.600 1Ch = 1.650 1Dh = 1.700 1Eh = 1.750 1Fh = 1.800 20h = 1.850 21h = 1.900 22h = 1.950 23h = 2.000 24h = 2.050 25h = 2.100 26h = 2.150 27h = 2.200 28h = 2.250 29h = 2.300 2Ah = 2.350 2Bh = 2.400 2Ch = 2.450 2Dh = 2.500 2Eh = 2.550 2Fh = 2.600 30h = 2.650 31h = 2.700 32h = 2.750 33h = 2.800 34h = 2.850 35h = 2.900 36h = 2.950 37h = 3.000 38h = 3.050 39h = 3.100 3Ah = 3.150 3Bh = 3.200 3Ch = 3.250 3Dh = 3.300 3Eh = 3.350 3Fh = 3.400 |
SEQ1 is shown in #TPS65218_SEQ1_FIGURE and described in #TPS65218_SEQ1_TABLE.
Return to Summary Table.
Password protected.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DLY8 | DLY7 | DLY6 | DLY5 | DLY4 | DLY3 | DLY2 | DLY1 |
| R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b | R/W-0b |
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | DLY8 | R/W, E2 | 0b |
Delay8 (occurs after Strobe 8 and before Strobe 9.) 0b = 2 ms 1b = 5 ms |
| 6 | DLY7 | R/W, E2 | 0b |
Delay7 (occurs after Strobe 7 and before Strobe 8.) 0b = 2 ms 1b = 5 ms |
| 5 | DLY6 | R/W, E2 | 0b |
Delay6 (occurs after Strobe 6 and before Strobe 7.) 0b = 2 ms 1b = 5 ms |
| 4 | DLY5 | R/W, E2 | 0b |
Delay5 (occurs after Strobe 5 and before Strobe 6.) 0b = 2 ms 1b = 5 ms |
| 3 | DLY4 | R/W, E2 | 0b |
Delay4 (occurs after Strobe 4 and before Strobe 5.) 0b = 2 ms 1b = 5 ms |
| 2 | DLY3 | R/W, E2 |
0b |
Delay3 (occurs after Strobe 3 and before Strobe 4.) 0b = 2 ms 1b = 5 ms |
| 1 | DLY2 | R/W, E2 |
0b |
Delay2 (occurs after Strobe 2 and before Strobe 3.) 0b = 2 ms 1b = 5 ms |
| 0 | DLY1 | R/W, E2 | 0b |
Delay1 (occurs after Strobe 1 and before Strobe 2.) 0b = 2 ms 1b = 5 ms |
SEQ2 is shown in #TPS65218_SEQ2_FIGURE and described in #TPS65218_SEQ2_TABLE.
Return to Summary Table.
Password protected.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DLYFCTR | RESERVED | DLY9 | |||||
| R/W -0b | R-000 000b | R/W -0b | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | DLYFCTR | R/W, E2 | 0b |
Power-down delay factor: 0b = 1x 1b = 10x (delay times are multiplied by 10x during power-down.) Note: DLYFCTR has no effect on power-up timing. |
| 6-1 | RESERVED | R | 000 000b | |
| 0 | DLY9 | R/W, E2 | 0b |
Delay9 (occurs after Strobe 9 and before Strobe 10.) 0b = 2 ms 1b = 5 ms |
SEQ3 is shown in #TPS65218_SEQ3_FIGURE and described in #TPS65218_SEQ3_TABLE.
Return to Summary Table.
Password protected.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DC2_SEQ | DC1_SEQ | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | DC2_SEQ | R/W, E2 | 0h |
DCDC2 enable STROBE: 0h = Rail is not controlled by sequencer. 1h = Rail is not controlled by sequencer. 2h = Rail is not controlled by sequencer. 3h = Enable at STROBE 3. 4h = Enable at STROBE 4. 5h = Enable at STROBE 5. 6h = Enable at STROBE 6. 7h = Enable at STROBE 7. 8h = Enable at STROBE 8. 9h = Enable at STROBE 9. Ah = Enable at STROBE 10. Bh = Rail is not controlled by sequencer. Ch = Rail is not controlled by sequencer. Dh = Rail is not controlled by sequencer. Eh = Rail is not controlled by sequencer. Fh = Rail is not controlled by sequencer. |
| 3-0 | DC1_SEQ | R/W, E2 | 0h |
DCDC1 enable STROBE: 0h = Rail is not controlled by sequencer. 1h = Rail is not controlled by sequencer. 2h = Rail is not controlled by sequencer. 3h = Enable at STROBE 3. 4h = Enable at STROBE 4. 5h = Enable at STROBE 5. 6h = Enable at STROBE 6. 7h = Enable at STROBE 7. 8h = Enable at STROBE 8. 9h = Enable at STROBE 9. Ah = Enable at STROBE 10. Bh = Rail is not controlled by sequencer. Ch = Rail is not controlled by sequencer. Dh = Rail is not controlled by sequencer. Eh = Rail is not controlled by sequencer. Fh = Rail is not controlled by sequencer. |
SEQ4 is shown in #TPS65218_SEQ4_FIGURE and described in #TPS65218_SEQ4_TABLE.
Return to Summary Table.
Password protected.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| DC4_SEQ | DC3_SEQ | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | DC4_SEQ | R/W, E2 | 0h |
DCDC4 enable STROBE: 0h = Rail is not controlled by sequencer. 1h = Rail is not controlled by sequencer. 2h = Rail is not controlled by sequencer. 3h = Enable at STROBE 3. 4h = Enable at STROBE 4. 5h = Enable at STROBE 5. 6h = Enable at STROBE 6. 7h = Enable at STROBE 7. 8h = Enable at STROBE 8. 9h = Enable at STROBE 9. Ah = Enable at STROBE 10. Bh = Rail is not controlled by sequencer. Ch = Rail is not controlled by sequencer. Dh = Rail is not controlled by sequencer. Eh = Rail is not controlled by sequencer. Fh = Rail is not controlled by sequencer. |
| 3-0 | DC3_SEQ | R/W, E2 | 0h |
DCDC3 enable STROBE: 0h = Rail is not controlled by sequencer. 1h = Rail is not controlled by sequencer. 2h = Rail is not controlled by sequencer. 3h = Enable at STROBE 3. 4h = Enable at STROBE 4. 5h = Enable at STROBE 5. 6h = Enable at STROBE 6. 7h = Enable at STROBE 7. 8h = Enable at STROBE 8. 9h = Enable at STROBE 9. Ah = Enable at STROBE 10. Bh = Rail is not controlled by sequencer. Ch = Rail is not controlled by sequencer. Dh = Rail is not controlled by sequencer. Eh = Rail is not controlled by sequencer. Fh = Rail is not controlled by sequencer. |
SEQ5 is shown in #TPS65218_SEQ5_FIGURE and described in #TPS65218_SEQ5_TABLE.
Return to Summary Table.
Password protected.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RESERVED | DC6_SEQ | RESERVED | DC5_SEQ | ||||
| R-0h | R/W-0h | R-0h | R/W-0h | ||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-6 | RESERVED | R | 0h | |
| 5-4 | DC6_SEQ | R/W, E2 | 0h |
DCDC6 enable STROBE. Note: STROBE 1 and STROBE 2 are executed only if FSEAL = 0. DCDC5 and 6 cannot be disabled by sequencer once freshness seal is broken. 0h = Rail is not controlled by sequencer. 1h = Enable at STROBE 1. 2h = Enable at STROBE 2. 3h = Rail is not controlled by sequencer. |
| 3-2 | RESERVED | R | 0h | |
| 1-0 | DC5_SEQ | R/W, E2 | 0h |
DCDC5 enable STROBE. Note: STROBE 1 and STROBE 2 are executed only if FSEAL = 0. DCDC5 and 6 cannot be disabled by sequencer once freshness seal is broken. 0h = Rail is not controlled by sequencer. 1h = Enable at STROBE 1. 2h = Enable at STROBE 2. 3h = Rail is not controlled by sequencer. |
SEQ6 is shown in #TPS65218_SEQ6_FIGURE and described in #TPS65218_SEQ6_TABLE.
Return to Summary Table.
Password protected.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LS1_SEQ | LDO1_SEQ | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | LS1_SEQ | R/W, E2 | 0h |
LS1 enable STROBE: 0h = Rail is not controlled by sequencer. 1h = Rail is not controlled by sequencer. 2h = Rail is not controlled by sequencer. 3h = Enable at STROBE 3. 4h = Enable at STROBE 4. 5h = Enable at STROBE 5. 6h = Enable at STROBE 6. 7h = Enable at STROBE 7. 8h = Enable at STROBE 8. 9h = Enable at STROBE 9. Ah = Enable at STROBE 10. Bh = Rail is not controlled by sequencer. Ch = Rail is not controlled by sequencer. Dh = Rail is not controlled by sequencer. Eh = Rail is not controlled by sequencer. Fh = Rail is not controlled by sequencer. |
| 3-0 | LDO1_SEQ | R/W, E2 | 0h |
LDO1 enable STROBE: 0h = Rail is not controlled by sequencer. 1h = Rail is not controlled by sequencer. 2h = Rail is not controlled by sequencer. 3h = Enable at STROBE 3. 4h = Enable at STROBE 4. 5h = Enable at STROBE 5. 6h = Enable at STROBE 6. 7h = Enable at STROBE 7. 8h = Enable at STROBE 8. 9h = Enable at STROBE 9. Ah = Enable at STROBE 10. Bh = Rail is not controlled by sequencer. Ch = Rail is not controlled by sequencer. Dh = Rail is not controlled by sequencer. Eh = Rail is not controlled by sequencer. Fh = Rail is not controlled by sequencer. |
SEQ7 is shown in #TPS65218_SEQ7_FIGURE and described in #TPS65218_SEQ7_TABLE.
Return to Summary Table.
Password protected.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| GPO3_SEQ | GPO1_SEQ | ||||||
| R/W-0h | R/W-0h | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7-4 | GPO3_SEQ | R/W, E2 |
0h |
GPO3 enable STROBE: 0h = Rail is not controlled by sequencer. 1h = Rail is not controlled by sequencer. 2h = Rail is not controlled by sequencer. 3h = Enable at STROBE 3. 4h = Enable at STROBE 4. 5h = Enable at STROBE 5. 6h = Enable at STROBE 6. 7h = Enable at STROBE 7. 8h = Enable at STROBE 8. 9h = Enable at STROBE 9. Ah = Enable at STROBE 10. Bh = Rail is not controlled by sequencer. Ch = Rail is not controlled by sequencer. Dh = Rail is not controlled by sequencer. Eh = Rail is not controlled by sequencer. Fh = Rail is not controlled by sequencer. |
| 3-0 | GPO1_SEQ | R/W, E2 | 0h |
GPO1 enable STROBE: 0h = Rail is not controlled by sequencer. 1h = Rail is not controlled by sequencer. 2h = Rail is not controlled by sequencer. 3h = Enable at STROBE 3. 4h = Enable at STROBE 4. 5h = Enable at STROBE 5. 6h = Enable at STROBE 6. 7h = Enable at STROBE 7. 8h = Enable at STROBE 8. 9h = Enable at STROBE 9. Ah = Enable at STROBE 10. Bh = Rail is not controlled by sequencer. Ch = Rail is not controlled by sequencer. Dh = Rail is not controlled by sequencer. Eh = Rail is not controlled by sequencer. Fh = Rail is not controlled by sequencer. |