Follow these layout guidelines:

• The IN_X pins should be bypassed to ground with a low ESR ceramic bypass capacitor. The typical recommended bypass capacitance is 4.7-µF with a X5R or X7R dielectric.
• The optimum placement is closest to the IN_X pins of the device. Take care to minimize the loop area formed by the bypass capacitor connection, the IN_X pin, and the thermal pad of the device.
• The thermal pad should be tied to the PCB ground plane with a minimum of 25 vias. See GUID-031D6EAF-7C5F-4080-8186-9AC29E57B1EA.html#T3834858-20 for an example.
• The LX trace should be kept on the PCB top layer and free of any vias.
• The FBX traces should be routed away from any potential noise source to avoid coupling.
• DCDC4 Output capacitance should be placed immediately at the DCDC4 pin. Excessive distance between the capacitance and DCDC4 pin may cause poor converter performance.