米6体育平台手机版

ZHCSNM6A May 2021 – August 2021 TPS6521855

PRODUCTION DATA

6.6 Timing Requirements

			MIN	NOM	MAX	UNIT
f_SCL	Serial clock frequency			100		kHz
f_SCL	Serial clock frequency			400		kHz
t_HD;STA	Hold time (repeated) START condition. After this period, the first clock pulse is generated.	SCL = 100 kHz	4			µs
t_HD;STA		SCL = 400 kHz	600			ns
t_LOW	LOW period of the SCL clock	SCL = 100 kHz	4.7			µs
t_LOW	LOW period of the SCL clock	SCL = 400 kHz	1.3			µs
t_HIGH	HIGH period of the SCL clock	SCL = 100 kHz	4			µs
t_HIGH	HIGH period of the SCL clock	SCL = 400 kHz⁽¹⁾	1			µs
t_SU;STA	Set-up time for a repeated START condition	SCL = 100 kHz	4.7			µs
t_SU;STA	Set-up time for a repeated START condition	SCL = 400 kHz	600			ns
t_HD;DAT	Data hold time	SCL = 100 kHz	0		3.45	µs
t_HD;DAT	Data hold time	SCL = 400 kHz	0		900	ns
t_SU;DAT	Data set-up time	SCL = 100 kHz	250			ns
t_SU;DAT	Data set-up time	SCL = 400 kHz	100			ns
t_r	Rise time of both SDA and SCL signals	SCL = 100 kHz			1000	ns
t_r	Rise time of both SDA and SCL signals	SCL = 400 kHz			300	ns
t_f	Fall time of both SDA and SCL signals	SCL = 100 kHz			300	ns
t_f	Fall time of both SDA and SCL signals	SCL = 400 kHz			300	ns
t_SU;STO	Set-up time for STOP condition	SCL = 100 kHz	4			µs
t_SU;STO	Set-up time for STOP condition	SCL = 400 kHz	600			ns
t_BUF	Bus free time between STOP and START condition	SCL = 100 kHz	4.7			µs
t_BUF	Bus free time between STOP and START condition	SCL = 400 kHz	1.3			µs
t_SP	Pulse width of spikes which must be suppressed by the input filter	SCL = 100 kHz	—⁽²⁾		—⁽²⁾	ns
t_SP		SCL = 400 kHz	0		50	ns
C_b	Capacitive load for each bus line	SCL = 100 kHz			400	pF
C_b	Capacitive load for each bus line	SCL = 400 kHz			400	pF

(1) The SCL duty cycle at 400 kHz must be > 40%.

(2) The inputs of I²C devices in Standard-mode do not require spike suppression.